LM98725 3 Ch, 16-Bit, 81 MSPS AFE w/LVDS/CMOS Output, CCD/CIS Sensor Timing

145 Pages·2015·5.77 MB·English

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LM98725
SNAS474H–APRIL2009–REVISEDMARCH2015
LM98725 3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/CMOS Output,
Integrated CCD/CIS Sensor Timing Generator and Spread Spectrum Clock Generation
1 Features 3 Description
• LVDS/CMOSOutputs The LM98725 is a fully integrated, high performance
1 16-Bit, 81 MSPS signal processing solution for digital
• LVDS/CMOS/CrystalClockSourcewithPLL
color copiers, scanners, and other image processing
Multiplication
applications. The LM98725 achieves high-speed
• IntegratedFlexibleSpreadSpectrumClock signal throughput with an innovative architecture
Generation utilizing Correlated Double Sampling (CDS), typically
employed with CCD arrays, or Sample and Hold
• CDSorS/HProcessingforCCDorCISSensors
(S/H) inputs (for higher speed CCD or CMOS image
• IndependentGain/OffsetCorrectionforEach
sensors). The signal paths utilize 8 bit Programmable
Channel
Gain Amplifiers (PGA), a ±9-Bit offset correction
• Automaticper-ChannelGainandOffset DAC, and independently controlled Digital Black
Calibration Level correction loops for each input. The
independently programmed PGA and offset DAC
• ProgrammableInputClampVoltage
allow unique values of gain and offset for each of the
• FlexibleCCD/CISSensorTimingGenerator
three analog inputs. The signals are then routed to a
81 MHz high performance analog-to-digital converter
2 Applications
(ADC). The fully differential processing channel
shows exceptional noise immunity with a very low
• Multi-FunctionPeripherals
noise floor of –74 dB. The 16-bit ADC has excellent
• High-speedCurrency/CheckScanners
dynamic performance making the LM98725
• FlatbedorHandheldColorScanners transparentintheimagereproductionchain.
• High-speedDocumentScanners
A very flexible integrated Spread Spectrum Clock
• KeySpecifications: Generation (SSCG) modulator is included to assist
– MaximumInputLevel withEMcomplianceandreducesystem costs.
– 1.2or2.4VoltModes
DeviceInformation(1)
– (Bothwith+or-PolarityOption)
PARTNUMBER PACKAGE BODYSIZE(NOM)
– ADCResolution:16-Bit
LM98725 TSSOP(56) 14.0mm×6.10mm
– ADCSamplingRate:81MSPS
(1) For all available packages, see the orderable addendum at
– INL:+17/-28LSB(typ) theendofthedatasheet.
– ChannelSamplingRate:30/30/27MSPS
SystemBlockDiagram
– PGAGain Steps:256Steps
CCD/CIS Sensor
– PGAGain Range:0.62to8.3x
Analog Front End
– AnalogDACResolution: ±9Bits SPI
– AnalogDACRange: ±307mVor ±614mV
LM98725 ImageA PSroICcessor/
– DigitalDACResolution: ±6Bits Sensor Drivers CGCeDn eTriamtoinrg Data Output
– DigitalDACRange:-2048LSBto+2016LSB CLK Motor
SSCG Controllers
– SNR: –74dB(@0dBPGAGain)
– PowerDissipation:755mW(LVDS)
– OperatingTemp:0to70°C
– SupplyVoltage:3.3VNominal(3.0-Vto3.6-V
Range)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
LM98725
SNAS474H–APRIL2009–REVISEDMARCH2015 www.ti.com
Table of Contents
1 Features.................................................................. 1 7.1 Overview.................................................................14
2 Applications........................................................... 1 7.2 FunctionalBlockDiagrams.....................................15
3 Description............................................................. 1 7.3 FeatureDescription.................................................16
7.4 DeviceFunctionalModes........................................24
4 RevisionHistory..................................................... 2
7.5 RegisterMaps.........................................................88
5 PinConfigurationandFunctions......................... 3
8 Layout................................................................. 136
6 Specifications......................................................... 6
8.1 LayoutExample....................................................136
6.1 AbsoluteMaximumRatings......................................6
9 DeviceandDocumentationSupport................ 137
6.2 HandlingRatings.......................................................6
9.1 Trademarks...........................................................137
6.3 RecommendedOperatingConditions.......................6
9.2 DeviceSupport......................................................137
6.4 ElectricalCharacteristics...........................................7
9.3 ElectrostaticDischargeCaution............................137
6.5 ACTimingSpecifications........................................11
9.4 Glossary................................................................137
6.6 SerialInterfaceTimingDetails................................13
10 Mechanical,Packaging,andOrderable
7 DetailedDescription............................................ 14
Information......................................................... 137
4 Revision History
NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionG(October2014)toRevisionH Page
• Changed"29"to"33"forPinnumber32inPinFunctions..................................................................................................... 4
• Deleted"Boldfacelimitsapply..."statementinElectricalCharacteristicsandACTimingSpecifications ............................. 7
• Changed"internal"to"external"and"external"to"internal"for"SH_RCaptureClockSelect(Page0,Register0x00,
Bit5)"headinginClockSources-AdditionalSettingsandFlexibility ................................................................................. 18
• Changed25MHzto27MHzand75MHzto81MHzforTable3 ...................................................................................... 24
• Changed"Page2"to"Page0"inCCDTimingGeneratorMaster/SlaveModes ................................................................ 63
• Changed"Page2"to"Page0"inMasterTimingGeneratorMode ..................................................................................... 63
• Changed"11000000"to"11000010"inTable18............................................................................................................ 101
ChangesfromRevisionF(January2014)toRevisionG Page
• Added,updated,orrenamedthefollowingsections:DeviceInformationTable,PinConfigurationandFunctions;
Layout;DeviceandDocumentationSupport;Mechanical,Packaging,andOrderingInformation ....................................... 1
• Added"Note"inSerialInterface........................................................................................................................................... 84
ChangesfromRevisionE(April2013)toRevisionF Page
• AddedcontentfromSystemOverviewsectiontoendofdocument. .................................................................................. 16
ChangesfromRevisionD(April2009)toRevisionE Page
• ChangedlayoutofNationalDataSheettoTIformat........................................................................................................... 13
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5 Pin Configuration and Functions
56-PinTSSOP
PackageDGG
TopView
PHIC2 1 56 SH5
PHIC1 2 55 SH4
SH1 3 54 PHIB2
CE 4 53 PHIB1
CAL 5 52 VC
RESET 6 51 DGND
SH_R 7 50 PHIA2
SDI 8 49 PHIA1
SDO 9 48 CP
SCLK 10 47 RS
SEN 11 46 SH3
VA 12 45 CLKOUT/SH2
AGND 13 56 Pin TSSOP 44 VC
VA 14 (not to scale) 43 VD
VREFB 15 42 DGND
VREFT 16 41 DOUT0/TXOUT0-
VA 17 40 DOUT1/TXOUT0+
AGND 18 39 DOUT2/TXOUT1-
VCLP 19 38 DOUT3/TXOUT1+
VA 20 37 DOUT4/TXOUT2-
IBIAS 21 36 DOUT5/TXOUT2+
AGND 22 35 DOUT6/TXCLK-
OSR 23 34 DOUT7/TXCLK+
AGND 24 33 INCLK-
OSG 25 32 INCLK+
AGND 26 31 DVB
OSB 27 30 CPOFILT1
CPOFILT2 28 29 DGND
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PinFunctions
PIN
I/O TYP RES DESCRIPTION
NO. NAME
1 PHIC2 O D Configurablehighspeedsensortimingoutput.
2 PHIC1 O D Configurablehighspeedsensortimingoutput.
3 SH1 O D Configurablelowspeedsensortimingoutput.
4 CE I D ChipSerialInterfaceAddressSettingInput
CELevel Address
VD 01
Float 10
DGND 00
5 CAL I D PD Initiatecalibrationsequence.LeaveunconnectedortietoDGNDifunused.
6 RESET I D PU Active-lowmasterreset.NCwhenfunctionnotbeingused.
7 SH_R I D PD ExternalrequestforanSHpulse.
8 SDI I D PD SerialInterfaceDataInput.CanbetiedtoSDOforcompatibilitywithLM98714designs.
9 SDO O D SerialInterfaceDataOutput.CanbetiedtoSDIforcompatibilitywithLM98714designs.
10 SCLK I D PD SerialInterfaceshiftregisterclock.
11 SEN I D PU Active-lowchipenablefortheSerialInterface.
12 V P Analogpowersupply.Bypassvoltagesourcewith4.7μFandpinwith0.1μFtoAGND.
A
13 AGND P Analoggroundreturn.
14 V P Analogpowersupply.Bypassvoltagesourcewith4.7μFandpinwith0.1μFtoAGND.
A
15 VREFB O A BottomofADCreference.Bypasswitha0.1μFcapacitortoground.
16 VREFT O A TopofADCreference.Bypasswitha0.1μFcapacitortoground.
17 V P Analogpowersupply.Bypassvoltagesourcewith4.7μFandpinwith0.1μFtoAGND.
A
18 AGND P Analoggroundreturn.
19 VCLP IO A InputClampVoltage.Normallybypassedwitha0.1μF,anda4.7μFcapacitortoAGND.
Anexternalreferencevoltagemaybeappliedtothispin.
20 V P Analogpowersupply.Bypassvoltagesourcewith4.7μFandpinwith0.1μFtoAGND.
A
21 IBIAS O A Biassettingpin.Connecta9.0kΩ1%resistortoAGND.
22 AGND P Analoggroundreturn.
23 OS I A Analoginputsignal.TypicallysensorRedoutputAC-coupledthruacapacitor.
R
24 AGND P Analoggroundreturn.
25 OS I A Analoginputsignal.TypicallysensorGreenoutputAC-coupledthruacapacitor.
G
26 AGND P Analoggroundreturn.
27 OS I A Analoginputsignal.TypicallysensorBlueoutputAC-coupledthruacapacitor.
B
28 CPOFILT2 A ChargePumpFilterCapacitor.Bypassthissupplypinwitha0.1μFcapacitorto
CPOFILT1.
29 DGND P Digitalgroundreturn.
30 CPOFILT1 A ChargePumpFilterCapacitor.
Bypassthissupplypinwitha0.1μFcapacitortoCPOFILT2.
31 DVB O D DigitalCoreVoltagebypass.Notaninput.Bypasswith0.1μFcapacitortoDGND.
32 INCLK+ I D ClockInput.
WhenXTALEN=0
Non-InvertinginputforLVDSclocksorCMOSclockinput.CMOSclockisselectedwhen
pin33isheldatDGND.OtherwiseclockisconfiguredforLVDSoperation.
WhenXTALEN=1
Connectiontoterminal2ofcrystal.
An18pFcapacitorshouldbeconnectedfromterminal1ofthecrystaltoground.
33 INCLK- I D ClockInput.
WhenXTALEN=0
InvertinginputforLVDSclocks,connecttoDGNDforCMOSclock.
WhenXTALEN=1
Connectiontoterminal1ofcrystal.A18pFcapacitorshouldbeconnectedfromterminal1
ofthecrystaltoground.
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PinFunctions (continued)
PIN
I/O TYP RES DESCRIPTION
NO. NAME
34 DOUT7/ O D Bit7ofthedigitalvideooutputbusinCMOSMode,LVDSFrameClock+inLVDSMode.
TXCLK+
35 DOUT6/ O D Bit6ofthedigitalvideooutputbusinCMOSMode,LVDSFrameClock-inLVDSMode.
TXCLK-
36 DOUT5/ O D Bit5ofthedigitalvideooutputbusinCMOSMode,LVDSDataOut2+inLVDSMode.
TXOUT2+
37 DOUT4/ O D Bit4ofthedigitalvideooutputbusinCMOSMode,LVDSDataOut2-inLVDSMode.
TXOUT2-
38 DOUT3/ O D Bit3ofthedigitalvideooutputbusinCMOSMode,LVDSDataOut1+inLVDSMode.
TXOUT1+
39 DOUT2/ O D Bit2ofthedigitalvideooutputbusinCMOSMode,LVDSDataOut1-inLVDSMode.
TXOUT1-
40 DOUT1/ O D Bit1ofthedigitalvideooutputbusinCMOSMode,LVDSDataOut0+inLVDSMode.
TXOUT0+
41 DOUT0/ O D Bit0ofthedigitalvideooutputbusinCMOSMode,LVDSDataOut0-inLVDSMode.
TXOUT0-
42 DGND O p Digitalgroundreturn.
43 V P Powersupplyforthedigitalcircuits.Bypassthissupplypinwith0.1μFcapacitor.Asingle
D
4.7μFcapacitorshouldbeusedbetweenthesupplyandtheVD,VRandVCpins.
44 V P Powersupplyforthesensorcontroloutputs.Bypassthissupplypinwith0.1μFcapacitor.
C
45 CLKOUT/SH2 O D OutputclockforregisteringoutputdatawhenusingCMOSoutputs,oraconfigurablelow
speedsensortimingoutput.
46 SH3 O D Configurablelowspeedsensortimingoutput.
47 RS O D Configurablehighspeedsensortimingoutput.
48 CP O D Configurablehighspeedsensortimingoutput.
49 PHIA1 O D Configurablehighspeedsensortimingoutput.
50 PHIA2 O D Configurablehighspeedsensortimingoutput.
51 DGND P Digitalgroundreturn.
52 V P Powersupplyforthesensorcontroloutputs.
C
Bypassthissupplypinwith0.1μFcapacitor.
53 PHIB1 O D Configurablehighspeedsensortimingoutput.
54 PHIB2 O D Configurablehighspeedsensortimingoutput.
55 SH4 O D Configurablelowspeedsensortimingoutput.
56 SH5 O D Configurablelowspeedsensortimingoutput.
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6 Specifications
6.1 Absolute Maximum Ratings(1)(2)(3)
MIN MAX UNIT
AnyPositiveSupplyVoltage(VA,VR,VD,VC) 4.2 V
VoltageonAnyInputorOutputPin(exceptDVB)(Nottoexceed4.2V) −0.3 4.2 V
DVBOutputVoltage 2.0 V
InputCurrentatanypin(4) ±25 mA
PackageInputCurrent(4) ±50 mA
PackageDissipationatT =25°C(5) 1.9 W
A
SolderingTemperature,Infrared,10seconds(6) 235 °C
(1) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsfor
whichthedeviceisfunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtestconditions,seethe
ElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmay
degradewhenthedeviceisnotoperatedunderthelistedtestconditions.OperationofthedevicebeyondtheOperatingRatingsisnot
recommended.
(2) AllvoltagesaremeasuredwithrespecttoA =D =0V,unlessotherwisespecified.
GND GND
(3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexasInstrumentsSalesOffice/Distributorsforavailabilityand
specifications.
(4) Whentheinputvoltage(V )atanypinexceedsthepowersupplies(V <GNDorV >V orV ),thecurrentatthatpinshouldbe
IN IN IN A D
limitedto25mA.The50mAmaximumpackageinputcurrentratinglimitsthenumberofpinsthatcansimultaneouslysafelyexceedthe
powersupplieswithaninputcurrentof25mAtotwo.
(5) Theabsolutemaximumjunctiontemperature(T )forthisdeviceis150°C.Themaximumallowablepowerdissipationisdictatedby
JMAX
T ,thejunctiontoambientthermalresistance(R ),andtheambienttemperature(TA),andcanbecalculatedusingtheformula
JMAX θJA
PDMAX=(T -TA)/R .ThevaluesformaximumpowerdissipationlistedwillbereachedonlywhentheLM98725isoperatedina
JMAX θJA
severefaultycondition.
(6) SeeAN450,“SurfaceMountingMethodsandTheirEffectonProductReliability”,orthesectionentitled“SurfaceMount”foundinany
post1986TexasInstrumentsSemiconductorLinearDataBook,forothermethodsofsolderingsurfacemountdevices.
6.2 Handling Ratings
MIN MAX UNIT
T Storagetemperaturerange −65 +150 °C
stg
Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all 2500
pins(2)
V Electrostaticdischarge(1) V
(ESD)
Chargeddevicemodel(CDM),perJEDECspecification 250
JESD22-C101,allpins(3)
(1) Humanbodymodelis100pFcapacitordischargedthrougha1.5-kΩresistor.Machinemodelis220-pFdischargedthrough0Ω.
(2) JEDECdocumentJEP155statesthat2500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
(3) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
6.3 Recommended Operating Conditions(1)(2)
MIN MAX UNIT
OperatingTemperatureRange 0≤T ≤+70 °C
A
AllSupplyVoltage +3.0 +3.6 V
(1) AbsoluteMaximumRatingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsindicateconditionsfor
whichthedeviceisfunctional,butdonotensurespecificperformancelimits.Forensuredspecificationsandtestconditions,seethe
ElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Someperformancecharacteristicsmay
degradewhenthedeviceisnotoperatedunderthelistedtestconditions.OperationofthedevicebeyondtheOperatingRatingsisnot
recommended.
(2) AllvoltagesaremeasuredwithrespecttoAGND=DGND=0V,unlessotherwisespecified.
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6.4 Electrical Characteristics
ThefollowingspecificationsapplyforVA=VD=VR=VC=3.3V,C =10pF,andf =27MHzunlessotherwise
L INCLK
specified.allotherlimitsT =25°C.(1)
A
PARAMETER TESTCONDITIONS MIN(2) TYP(3) MAX(2) UNIT
CMOSDIGITALINPUTDCSPECIFICATIONS(RESETb,SH_R,SCLK,SENb)
V Logical“1”InputVoltage 2.0 V
IH
V Logical“0”InputVoltage 0.8 V
IL
V LogicInputHysteresis 0.6 V
IHYST
V =VD:
IH
RESET,SEN 100 nA
I Logical“1”InputCurrent
IH
SH_R,SCLK,SDI,CAL 65
μA
CE 30
V =DGND:
IL
RESET,SEN –65 μA
I Logical“0”InputCurrent
IL
SH_R,SCLK,SDI,CAL –100 nA
CE –30 μA
CMOSDIGITALOUTPUTDCSPECIFICATIONS(SH1toSH5,RS,CP,PHIA,PHIB,PHIC)
V Logical“1”OutputVoltage I =-0.5mA 3.0 V
OH OUT
V Logical“0”OutputVoltage I =1.6mA 0.21 V
OL OUT
I OutputShortCircuitCurrent V =DGND 18
OS OUT
mA
V =VD –25
OUT
I CMOSOutputTRI-STATE V =DGND 20
OZ OUT
Current nA
V =VD –25
OUT
CMOSDIGITALOUTPUTDCSPECIFICATIONS(CMOSDATAOUTPUTS)
V Logical“1”OutputVoltage I =-0.5mA 2.3 V
OH OUT
V Logical“0”OutputVoltage I =1.6mA 0.12 V
OL OUT
I OutputShortCircuitCurrent V =DGND 12
OS OUT
mA
V =VD –14
OUT
I CMOSOutputTRI-STATE V =DGND 20
OZ OUT
Current nA
V =VD –25
OUT
LVDS/CMOSCLOCKRECEIVERDCSPECIFICATIONS(INCLK+andINCLK-PINS)
V DifferentialLVDSClock
IHL
200 mV
HighThresholdVoltage R =100Ω
L
VILL DifferentialLVDSClock VCM(LVDSInputCommonModeVoltage)=1.25V
–200 mV
LowThresholdVoltage
V CMOSClock
IHC
2.0 V
HighThresholdVoltage
INCLK-=DGND
V CMOSClock
ILC
0.8 V
LowThresholdVoltage
I CMOSClock
IHL
230 260 μA
InputHighCurrent
I CMOSClock
ILC
–135 –120 μA
InputLowCurrent
(1) TheanaloginputsareprotectedasshowninFigure2.Inputvoltagemagnitudesbeyondthesupplyrailswillnotdamagethedevice,
providedthecurrentislimitedperNote4undertheAbsoluteMaximumRatingsTable.However,inputerrorswillbegeneratedIfthe
inputgoesaboveVAandbelowAGND.
(2) TestlimitsarespecifiedtoTexasInstruments'AOQL(AverageOutgoingQualityLevel).
(3) TypicalfiguresareatT =25°C,andrepresentmostlikelyparametricnormsatthetimeofproductcharacterization.Thetypical
A
specificationsarenotensured.
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Electrical Characteristics (continued)
ThefollowingspecificationsapplyforVA=VD=VR=VC=3.3V,C =10pF,andf =27MHzunlessotherwise
L INCLK
specified.allotherlimitsT =25°C.(1)
A
PARAMETER TESTCONDITIONS MIN(2) TYP(3) MAX(2) UNIT
LVDSOUTPUTDCSPECIFICATIONS
V DifferentialOutputVoltage R =100Ω 280 390 490 mV
OD L
V LVDSOutputOffsetVoltage 1.08 1.20 1.33 V
OS
I OutputShortCircuitCurrent V =0V,R =100Ω 8.5 mA
OS OUT L
POWERSUPPLYSPECIFICATIONS
LVDSOutputDataFormat 152 180 mA
LVDSOutputDataFormat
3.6 6 mA
IA VAAnalogSupplyCurrent (Powerdown)
CMOSOutputDataFormat
136 168 mA
(40MHz)
LVDSOutputDataFormat 76 94 mA
LVDSOutputDataFormat
VDDigitalOutputDriver 8.5 17 mA
ID (Powerdown)
SupplyCurrent
CMOSOutputDataFormat
46 68 mA
(ATELoadingofCMOSOutputs>50pF)(40MHz)
VCCCDTimingGenerator Typicalsensoroutputs:SH1-SH5,PHIA,PHIB,PHIC,
IC 1 4 mA
OutputDriverSupplyCurrent RS,CP(ATELoadingofCMOSOutputs>50pF)
LVDSOutputDataFormat 755 885 mW
LVDSOutputDataFormat
40 70 mW
PWR AveragePowerDissipation (Powerdown)
CMOSOutputDataFormat
600 740 mW
(ATELoadingofCMOSOutputs>50pF)(40MHz)
INPUTSAMPLINGCIRCUITSPECIFICATIONS
CDSGain=1x,PGAGain=1x 2.3
V InputVoltageLevel Vp-p
IN
CDSGain=2x,PGAGain=1x 1.22
SourceFollowersOff
32
CDS/SHGain=1x (–200) 50 μA
(-165)
OS =VA(OS =AGND)
X X
SampleandHoldMode SourceFollowersOff
55
I InputLeakageCurrent CDS/SHGain=2x (–290) 70 μA
IN_SH (–240)
(Vclamp=Default=2.6V) OS =VA(OS =AGND)
X X
SourceFollowersOn
20
CDS/SHGain=2x (–250) 250 nA
(–50)
OS =VA(OS =AGND)
X X
Sample/HoldMode CDSGain=1x 2.5 pF
C EquivalentInputCapacitance
SH (seeFigure12) CDSGain=2x 4 pF
CDSMode SourceFollowersOff 10
I (–250) 250 nA
IN_CDS InputLeakageCurrent OS =VA(OS =AGND) (–50)
X X
CLPINSwitchResistance
R (OS toVCLPNodein 16 55 Ω
CLPIN X
Figure9)
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Electrical Characteristics (continued)
ThefollowingspecificationsapplyforVA=VD=VR=VC=3.3V,C =10pF,andf =27MHzunlessotherwise
L INCLK
specified.allotherlimitsT =25°C.(1)
A
PARAMETER TESTCONDITIONS MIN(2) TYP(3) MAX(2) UNIT
VCLPREFERENCECIRCUITSPECIFICATIONS
VCLPVoltage000 VCLPVoltageSetting=000 0.85VA V
VCLPVoltage001 VCLPVoltageSetting=001 0.9VA V
VCLPVoltage010 VCLPVoltageSetting=010 0.95VA V
VCLPVoltage011 VCLPVoltageSetting=011 0.6VA V
V
VCLP
VCLPVoltage100 VCLPVoltageSetting=100 0.55VA V
VCLPVoltage101 VCLPVoltageSetting=101 0.4VA V
VCLPVoltage110 VCLPVoltageSetting=110 0.35VA V
VCLPVoltage111 VCLPVoltageSetting=111 0.15VA V
I VCLPDACShortCircuit mA
SC 30
OutputCurrent
BLACKLEVELOFFSETDACSPECIFICATIONS
Resolution 10 Bits
Monotonicity Ensuredby
characterization
CDSGain=1x
MinimumDACCode=0x000 –614 mV
OffsetAdjustmentRange MaximumDACCode=0x3FF 614
ReferredtoAFEInput CDSGain=2x
MinimumDACCode=0x000 –307 mV
MaximumDACCode=0x3FF 307
OffsetAdjustmentRange MinimumDACCode=0x000 –17500 –16130
LSB
ReferredtoAFEOutput MaximumDACCode=0x3FF +16130 +17500
CDSGain=1x 1.2 mV
DACLSBStepSize ReferredtoAFEOutput
(32) (LSB)
DNL +0.74/ LSB
DifferentialNon-Linearity –0.84 +2.4
–0.37
INL +0.72/ LSB
IntegralNon-Linearity –2.5 +2.5
–0.56
PGASPECIFICATIONS
GainResolution 8 Bits
Ensuredby
Monotonicity
characterization
CDSGain=1x 7.7 8.3 8.8 V/V
MaximumGain
CDSGain=1x 17.7 18.4 18.9 dB
CDSGain=1x 0.58 0.62 0.67 V/V
MinimumGain
CDSGain=1x –4.7 –4.2 –3.5 dB
Gain(V/V)=(180/(277-PGACode))
PGAFunction
Gain(dB)=20LOG10(180/(277-PGACode))
MinimumPGAGain 3%
ChannelMatching
MaximumPGAGain 12.7%
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Electrical Characteristics (continued)
ThefollowingspecificationsapplyforVA=VD=VR=VC=3.3V,C =10pF,andf =27MHzunlessotherwise
L INCLK
specified.allotherlimitsT =25°C.(1)
A
PARAMETER TESTCONDITIONS MIN(2) TYP(3) MAX(2) UNIT
ADCSPECIFICATIONS
V TopofReference 2.07 V
REFT
V BottomofReference 0.89 V
REFB
V - V
REFT DifferentialReferenceVoltage 1.06 1.18 1.30
V
REFB
OverrangeOutputCode 65535
UnderrangeOutputCode 0
DIGITALOFFSET“DAC”SPECIFICATIONS
Resolution 7 Bits
DigitalOffsetDACLSBStep ReferredtoAFEOutput LSB
32
Size
MinDACCode=7'b0000000 –2048
OffsetAdjustmentRange
MidDACCode=7'b1000000 0 LSB
ReferredtoAFEOutput
MaxDACCode=7'b1111111 +2016
FULLCHANNELPERFORMANCESPECIFICATIONS
DNL See (4) +0.8/ LSB
DifferentialNon-Linearity -0.999 2.5
–0.7
INL See (4) +18/ LSB
IntegralNon-Linearity –75 75
–25
–76 dB
MinimumPGAGain(4) LSB
10 26
RMS
SNR TotalOutputNoise
–56 dB
MaximumPGAGain(4) LSB
96
RMS
Mode3 26
ChanneltoChannelCrosstalk LSB
Mode2 17
(4) Thisparameterensuredbydesignandcharacterization.
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