Journal of Systems Architecture 2000: Vol 46 Index

12 Pages·2000·2.5 MB·English

JOURNAL OF
SYSTEMS
ARCHITECTURE
ELSEVIER Journal of Systems Architecture 46 (2000) 1487-1491
www.elsevier.com/locate/sysarc
Author index to volume 46 (2000)
Abd El-Baky, M.A., see Moharam, H. 1073-1091 Bandyopadhyay, S., see Maulik, U. 297-300
Abdulla, M.F., C.P. Ravikumar and A. Kumar, Bandyopadhyay, J., Bandyopadhyay A.K., On
A scheme for multiple on-chip signature the derivation of a correct deadlock free
checking for embedded SRAMS 181-199 communication kernel for loop connected
Ahn, G.-J., Role-based access control in DCOM _ 1175-1184 message passing architecture from its user’s
Ajmone Marsan, M., F. Neri, C. Scarpati Cioffari specification 1257-1261
and A. Vasco, GSPN models of bridged LAN Bardsley, A. and D. Edwards, Synthesising an
configurations 105-130 asynchronous DMA controller with Balsa 1309-1319
Al-Houmaily, Y.J. and P.K. Chrysanthis, An Bartlett, P., see Parameswaran, S. 1263-1274
atomic commit protocol for gigabit-net- Bhattacharya, S. and M. Nasipuri, Traffic analy-
worked distributed database systems 809-833 sis in a double grain Dataflow array processor 97-101
Al-Massarani, A., see Al-Mouhamed, M. 851-871 Bhattacharyya, S., see Maulik, U. 297-300
Al-Mouhamed, M. and A. Al-Massarani, Sche- Bina, T.C., see Vidya, D. 1275-1291
duling optimization through iterative refine- Bondavalli, A., see Burns, A. 305-325
ment 851-871 Boni, A., see Anguita, D. 429-438
Al-Shoshan, A. and M. AlOgeely, Systolic arrays Buonanno, G., F. Fummi and D. Sciuto, An
architecture for computing the time-frequency extended-UIO-based method for protocol
spectrum 513-517 conformance testing 225-242
Ali, S., see Siegel, H.J. 627-639 Burns, A., D. Prasad, A. Bondavalli, F. Di
Allahverdi, N.M., Sirzad §. Kahramanli and Giandomenico, K. Ramamritham, J. Stanko-
K. Erciyes, A fault tolerant routing algo- vic and L. Strigini, The meaning and role of
rithm based on cube algebra for hypercube value in scheduling flexible real-time systems 305-325
systems 201-205 Burns, A., see McElhone, C. 49-77
AlMojel, A.I., T. El-Ghazawi and T. Sterling, Busquets-Mataix, J.V., D. Gil, P. Gil and A.
Characterizing and representing workloads Wellings, Techniques to increase the schedul-
for parallel computer architectures 23-37 able utilization of cache-based preemptive
AlOgeely, M., see Al-Shoshan, A. 513-517 real-time systems 357-378
Altenbernd, P., see Stappert, F. 339-355 Buttazzo, G., see Lipari, G. 327-338
Anguita, D., A. Boni and G. Parodi, A case study
of a distributed high-performance computing
system for neurocomputing 429-438 Cabaleiro, J.C., see Gonzalez, P. 675-685
Aweya, J., On the design of IP routers Part 1: Cabodi, G., P. Camurati and S. Quer, Symbolic
Router architectures 483-511 forward/backward traversals of large finite
Ayani, R., see Vlassov, V. 1205-1230 state machines 1137-1158
1383-7621/00/$ - see front matter © 2000 Elsevier Science B.V. All rights reserved.
PII: S1383-7621(00)00043-6
1488 Author index | Journal of Systems Architecture 46 (2000) 1487-1491
Cabri, G., L. Leonardi and F. Zambonelli, Drechsler, R., see Giinther, W. 1321-1334
Agents for information retrieval: Issues of Duato, J., see Malumbres, M.P. 1019-1032
mobility and coordination 1419-1433
Camurati, P., see Cabodi, G. 1137-1158 Edwards, D., see Bardsley, A. 1309-1319
Castorino, A. and G. Ciccarella, Algorithms Eeckhout, L., H. Neefs and K. De Bosschere,
for real-time scheduling of error-cumulative Early design stage exploration of fixed-length
tasks based on the imprecise computation block structured architectures 1469-1486
approach 587-600 El-Ghazawi, T., see AlMojel, A.I. 23-37
Chang, C.-Y., see Chen, T.-S. 919-930 Elston, C.J., see Davis, S.J. 749-764
Chang, J.-W., see Kim, J.-K. 655-673 Ercan, M.F., Y.-F. Fung and M.S. Demokan,
Chantrapornchai, C., E.H.-M. Sha and X. Communication in a multi-layer MIMD
(Sharon) Hu, Efficient module selections for system for computer vision 1349-1364
finding highly acceptable designs based on Erciyes, K., see Kahramanli, Sirzad §S. 201-205
inclusion scheduling 1047-1071
Chen, T.-S., C.-Y. Chang and J.-P. Sheu, Fagot, A., see de Kergommeaux, J.C. 835-849
Efficient path-based multicast in wormhole- Findlay, P.A., see Davis, S.J. 749-764
routed mesh networks 919-930 Foris, T., see Szirmay-Kalos, L. 275-296
Cheung, T.-Y., see Guan, H. 1185-1190 Fummi, F., see Buonanno, G. 225-242
Cho, K.R., see Kwon, S.K. 131-144 Fung, Y.-F., see Fikret Ercan, M. 1349-1364
Choi, G., see Jeon, J. 1403-1418
Chrysanthis, P.K., see Al-Houmaily, Y.J. 809-833 Garcia, D.F., see Suarez, F.J. 931-949
Ciccarella, G., see Castorino, A. 587-600 Garcia, J., see Suarez, F.J. 931-949
Clematis, A., G. Dodero and V. Gianuzzi, Garcia, J.M., see Sanchez, J.L. 873-888
Efficient use of parallel libraries on hetero- Gianuzzi, V., see Clematis, A. 641-653
geneous Networks of Workstations 641-653 Gil, D., see Busquets-Mataix, J.V. 357-378
Gil, P., see Busquets-Mataix, J.V. 357-378
da Silva Fraga, J., see de Oliveira, R.S. 991-1004 Gonsalves, T.A., see Venkatesulu, D. 411-428
Das, N., K. Mukhopadhyaya and J. Dattagupta, Gonzalez, P., J.C. Cabaleiro and T.F. Pena, On
O(n) routing in rearrangeable networks 529-542 parallel solvers for sparse triangular systems 675-685
Dattagupta, J., see Das, N. 529-542 Goutis, C.E., see Masselos, K. 551-571
Davis, S.J., C.J. Elston and P.A. Findlay, Guan, H. and T.-Y. Cheung, Efficient ap-
Register bypassing in an asynchronous super- proaches for constructing a massively parallel
scalar processor 749-764 processing system 1185-1190
De Almeida, D. and P. Kellert, Markovian and Giinther, W. and R. Drechsler, ACTion: Com-
analytical models for multiple bus multi- bining logic synthesis and technology map-
processor systems with memory blockings 455-477 ping for MUX-based FPGAs 1321-1334
De Bosschere, K., see Eeckhout, L. 1469-1486
de Kergommeaux, J.C. and A. Fagot, Execution Hamalainen, T., see Kolinummi, P. 955-972
replay of parallel procedural programs 835-849 Han, T.-D., see Kim, Y. 259-274
de Oliveira, R.S. and J. da Silva Fraga, Fixed priority Hariram, R.K., see Venkatesulu, D. 411-428
scheduling of tasks with arbitrary precedence Havinga, P.J.M. and GJ.M. Smit, Design
constraints in distributed hard real-time systems 991-1004 techniques for low-power systems 1-21
DeBrunner, L.S., see Racherla, G. 951-954 Hong, W.-K. and S.-D. Kim, A section cache
Demokan, M.S., see Ercan, M.F. 1349-1364 system designed for VLIW architectures 1293-1308
Di Giandomenico, F., see Burns, A. 305-325 Hong, W.-K., see Lee, J.-S. 1365-1382
Ding, J.-W., see Tsao, S.-L. 163-179 Horvath, T., see Szirmay-Kalos, L. 275-296
Djemal, R., G. Mazaré and R. Tourki, Rapid Hsiung, P.-A., Embedded software verification in
prototyping of an ATM programmable asso- hardware-software codesign 1435-1450
Ciative operator 1159-1173 Hsu, W.W., see Peir, J.-K. 439-454
Dodero, G., see Clematis, A. 641-653 Huang, Y.-M., see Tsao, S.-L. 163-179
4
Author index | Journal of Systems Architecture 46 (2000) 1487-1491 1489
Hwang, K.., see Jin, H. 543-550 ory-processor integrated architecture for
Hwang, W.-S., see Wang, W.-F. 1115-1135 computer vision 259-274
Hyun, J., see Jung, I. 1191-1204 Knowles, A.E., see Ki, A. 1093-1102
Kolinummi, P., T. Hamalainen and J. Saarinen,
Jang, I., see Song, H. 1005-1012 Chained backplane communication architec-
Jeon, H.G., see Kwon, S.K. 131-144 ture for scalable multiprocessor systems 955-972
Jeon, J., H.-S. Kim, G. Choi and H. Park, Kumar, A., see Abdulla, M.F. 181-199
KAIST image computing system (KICS): A Kwon, B., see Song, H. 1005-1012
parallel architecture for real-time multimedia Kwon, S.K., H.G. Jeon and K.R. Cho, Optimum
data processing 1403-1418 reserved resource allocation scheme for hand-
Jin, H. and K. Hwang, Stripped mirroring RAID off in CDMA cellular system
architecture 543-550
Jung, I. and S. Moon, Transaction multicasting
Lam, K.-y. and J. Kee-Yin Ng, A conditional
scheme for resilient routing control in parallel
abortable priority ceiling protocol for sche-
cluster database systems 699-719
duling mixed real-time tasks 573-585
Jung, I., J. Hyun and J. Lee, A scheduling policy
Lee, J., see Jung, I. 1191-1204
for preserving cache locality in a multipro-
Lee, J., see Rhee, Y. 903-918
grammed system 1191-1204
Lee, J.-H., J.-S. Lee and S.-D. Kim, A new cache
architecture based on temporal and spatial
Kahramanli, Sirzad §., N.M., Sirzad_ S.
locality 1451-1467
Kahramanli and K. Erciyes, A fault tolerant
Lee, J.-S., see Lee, J.-H. 1451-1467
routing algorithm based on cube algebra for
Lee, J.-S., W.-K. Hong and S.-D. Kim, An on-
hypercube systems 201-205
chip cache compression technique to reduce
Kang, S. and S. Moon, Read-down conflict-
decompression overhead and design complex-
preserving serializability as a correctness
ity 1365-1382
criterion for multilevel-secure optimistic con-
Lee, K.-W., see Lee, N.-K. 1383-1402
currency control: CSR/RD 889-902
Lee, N.-K., S.-B. Yang and K.-W. Lee, Efficient
Kaxiras, S., Distributed vector architectures 973-990
parity placement schemes for tolerating up to
Kee-Yin Ng, J., see Lam, K.-y. 573-585
two disk failures in disk arrays 1383-1402
Kellert, P., see De Almeida, D. 455-477
Leonardi, L., see Cabri, G. 1419-1433
Khalid, H., Performance evaluation of system
Lipari, G. and G. Buttazzo, Schedulability
architectures with validated input data 1013-1017
analysis of periodic and aperiodic tasks with
Khalid, H., Validation of SPEC6™ CFP95 traces
resource constraints 327-338
for accurate performance evaluation of com-
Loh, K.S. and W.F. Wong, Multiple context
puter systems 619-623
multithreaded superscalar processor architec-
Khanna, V.K., A novel approach for implementing
ture 243-258
high-speed and long-distance networking pro-
Loucif, S. and M. Ould-Khaoua, On the relative
tocols in a limited memory embedded kernel 1335-1348
performance merits of hypercube and hyper-
Ki, A. and A.E. Knowles, Stride prefetching for
mesh networks 1103-1114
the secondary data cache 1093-1102
Kim, H.-S., see Jeon, J. 1403-1418
Kim, J.-K. and J.-W. Chang, Vertically-parti- Mackenzie, L.M., see Ould-Khaoua, M. 779-792
tioned parallel signature file method 655-673 Maeng, S.R., see Yoo, D. 765-778
Kim, S.-D., see Hong, W.-K. 1293-1308 Malumbres, M.P. and J. Duato, An efficient
Kim, S.-D., see Kim, Y. 259-274 implementation of tree-based multicast rout-
Kim, S.-D., see Lee, J.-H. 1451-1467 ing for distributed shared-memory multipro-
Kim, S.-D., see Lee, J.-S. 1365-1382 cessors 1019-1032
Kim, Y., T.-D. Han and S.-D. Kim, Impact of Manimaran, G., see Mittal, A. 793-807
the memory interface structure in the mem- Marton, G., see Szirmay-Kalos, L. 275-296
1490 Author index / Journal of Systems Architecture 46 (2000) 1487-1491
Masselos, K., P. Merakos, T. Stouraitis and C.E. Park, H., see Jeon, J. 1403-1418
Goutis, Low power architectures for digital Park, I., see Yoo, D. 765-778
signal processing 551-571 Parkinson, M.F., see Parameswaran, S. 1263-1274
Maulik, U., S. Bandyopadhyay and S. Bhatta- Parodi, G., see Anguita, D. 429-438
charyya, Fault tolerant permutation mapping Parthasarathy, R., see Vidya, D. 1275-1291
in multistage interconnection network 297-300 Peir, J.-K., W.W. Hsu, H. Young and S. Ong,
Mazaré, G., see Djemal, R. 1159-1173 Improving cache performance with Full-Map
McElhone, C. and A. Burns, Scheduling optional Block Directory 439-454
computations for adaptive real-time systems 49-77 Pena, T.F., see Gonzalez, P. 675-685
Merakos, P., see Masselos, K. 551-571 Peng, Z., see Yang, T. 209-223
Mittal, A., G. Manimaran and C. Siva Ram Pombortsis, A., see Veglis, A. 39-47
Murthy, Integrated dynamic scheduling of Pountourakis, I.E., Optimal bandwidth alloca-
hard and QoS degradable real-time tasks in tion and stability of high-speed networks for
multiprocessor systems 793-807 CSMA/CD protocols 1253-1256
Moharam, H., M.A. Abd El-Baky and S.M.M. Prasad, D., see Burns, A. 305-325
Nassar, YOMNA - An efficient deadlock-free Puliafito, A., O. Tomarchio and L. Vita, MAP:
multicast wormhole algorithm in 2-D mesh design and implementation of a mobile
multicomputers 1073-1091 agents’ platform 145-162
Molano, A., A. Vina and R. Rajkumar, Operat-
ing system support for the management of Quer, S., see Cabodi, G. 1137-1158
hard real-time disk traffic 379-395
Moon, S., see Jung, I. 699-719 Racherla, G., S. Radhakrishnan and L.S. De
Moon, S., see Kang, S. 889-902 Brunner, Parameterization of _ efficient
Moon, S., see Sohn, K. 687-698 dynamic reconfigurable trees 951-954
Mukhopadhyaya, K., see Das, N. 529-542 Radhakrishnan, S., see Racherla, G. 951-954
Rajkumar, R., see Molano, A. 379-395
Nasipuri, M., see Bhattacharya, S. 97-101 Ramamritham, K., see Burns, A. 305-325
Nassar, S.M.M., see Moharam, H. 1073-1091 Ravikumar, C.P., see Abdulla, M.F. 181-199
Navet, N., Y.-Q. Song and F. Simonot, Worst- Rhee, Y. and J. Lee, Broadcast directory: A
case deadline failure probability in real-time scalable cache coherent architecture for mesh-
applications distributed over controller area connected multiprocessors 903-918
network 607-617 Romanovsky, A., Extending conventional lan-
Neefs, H., see Eeckhout, L. 1469-1486 guages by distributed/concurrent exception
Neri, F., see Ajmone Marsan, M. 105-130 resolution 79-95
Oehring, H., U. Sigmund and T. Ungerer, Saarinen, J., see Kolinummi, P. 955-972
Performance of simultaneous multithreaded Sanchez, J.L. and J.M. Garcia, Dynamic reconfi-
multimedia-enhanced processors for MPEG-2 guration of node location in wormhole net-
video decompression 1033-1046 works 873-888
Ong, S., see Peir, J.-K. 439-454 Santos, J., see Santos, R.M. 601-605
Orozco, J., see Santos, R.M. 601-605 Santos, R.M., J. Santos, J. Orozco and M.
Ould-Khaoua, M. and L.M. Mackenzie, On the Zambon, Real-time multimedia standards in
design of hypermesh interconnection net- DQDB 601-605
works for multicomputers 779-792 Sato, T., Quantitative evaluation of pipelining
Ould-Khaoua, M., see Loucif, S. 1103-1114 and decoupling a dynamic instruction sche-
duling mechanism 1231-1252
Papaefstathiou, E., see Veglis, A. 39-47 Scarpati Cioffari, C., see Ajmone Marsan, M. 105—130
Parameswaran, S., M.F. Parkinson and P. Sciuto, D., see Buonanno, G. 225-242
Bartlett, Profiling in the ASP codesign envir- Sha, E.H.-M., see Chantrapornchai, C. 1047-1071
onment 1263-1274 (Sharon) Hu, X., see Chantrapornchai, C. 1047-1071
Author index | Journal of Systems Architecture 46 (2000) 1487-1491
Sheu, J.-P., see Chen, T.-S. 919-930 Tyrrell, A.M. and S.L. Smith, Heterogeneous
Siegel, H.J. and S. Ali, Techniques for mapping distributed and parallel architectures: Hard-
tasks to machines in heterogeneous comput- ware, software and design tools 625-626
ing systems 627-639
Sigmund, U., see Oehring, H. 1033-1046
Ungerer, T., see Oehring, H. 1033-1046
Simonot, F., see Navet, N. 607-617
Siva Ram Murthy, C., see Mittal, A. 793-807
Vasco, A., see Ajmone Marsan, M. 105—130
Smit, G.J.M., see Havinga, P.J.M. 1-21
Veglis, A., A. Pombortsis and E. Papaefstathiou,
Smith, S.L., see Tyrrell, A.M. 625-626
Performance evaluation of a bus-based multi-
Sohn, K. and S. Moon, Achieving high degree of
stage multiprocessor architecture 39-47
concurrency in multidatabase transaction
Venkatesulu, D., T.A. Gonsalves and R.K.
scheduling: MTOS 687-698
Hariram, On the performance of distributed
Son, S.H., Issues and approaches to supporting
objects 411-428
timeliness and security in real-time database
Vina, A., see Molano, A. 379-395
systems 397-410
Vidya, D., R. Parthasarathy, T.C. Bina and N.G.
Song, H., B. Kwon, I. Jang and H. Yoon, An
Swaroopa, Architecture for fractal image
output queueing analysis of multipath ATM
compression 1275-1291
switches 1005-1012
Vita, L., see Puliafito, A. 145-162
Song, Y.-Q., see Navet, N. 607-617
Vlassov, V. and R. Ayani, Analytical modeling of
Stankovic, J., see Burns, A. 305-325
multithreaded architectures 1205-1230
Stappert, F. and P. Altenbernd, Complete worst-
case execution time analysis of straight-line
hard real-time programs 339-355 Wang, D., The diagnosability of hypercubes with
arbitrarily missing links 519-527
Steininger, A., Testing and built-in self-test — A
Wang, J.-Y., see Wang, W.-F. 1115-1135
survey 721-747
Sterling, T., see AlMojel, A.I. 23-37 Wang, W.-F., W.-S. Hwang and J.-Y. Wang,
Stouraitis, T., see Masselos, K. 551-571 Design of a large-scale Gbit/s MAN using a
Strigini, L., see Burns, A. 305-325 cyclic reservation-based MAC protocol 1115-1135
Wellings, A., see Busquets-Mataix, J.V. 357-378
Suarez, F.J., D.F. Garcia and J. Garcia, Mea-
Wong, W.F., see Loh, K.S. 243-258
surement based analysis of temporal beha-
viour as support for scheduling problems in
parallel and distributed real-time systems 931-979 Yang, S.-B., see Lee, N.-K. 1383-1402
Swaroopa, N.G., see Vidya, D. 1275-1291 Yang, T. and Z. Peng, An improved register—
Szirmay-Kalos, L., G. Marton, T. Foris and transfer level functional partitioning ap-
T. Hornath, Development of process Visua- proach for testability 209-223
lization systems: An object-oriented approach 275-296 Yoo, D., I. Park and S.R. Maeng, Multistage
ring network: An interconnection network for
large scale shared memory multiprocessors 765-778
Tomarchio, O., see Puliafito, A. 145-162 Yoon, H., see Song, H. 1005-1012
Tourki, R., see Djemal, R. 1159-1173 Young, H., see Peir, J.-K. 439-454
Tsao, S.-L., Y.-M. Huang and J.-W. Ding,
Performance analysis of video storage server Zambon, M., see Santos, R.M. 601-605
under initial delay bounds 163-179 Zambonelli, F., see Cabri, G. 1419-1433

JOURNAL OF
SYSTEMS
ARCHITECTURE
ELSEVIER Journal of Systems Architecture 46 (2000) 1493-1497
www.elsevier.com/locate/sysarc
Subject index to volume 46 (2000)
2-D mesh topology 1073 Cache 1093, 1293
Acceptable designs 1047 Cache access time 439
Ada 83 79 Cache architecture 1365
Ada 95 79 Cache coherence 903
Adaptive policy 397 Cache locality 1185
Adaptive routing 1103 Cache memories 357
Algorithm mapping 259 Cache memory 339, 439
Algorithms 951 Cache partitioning 357
Aliasing 181 Cache simulation 1451
Analysis methodology 931 CAN 607
Analytical model 1205 CDMA 131
Application design 1419 Cellular system 131
Approximate analytical models 455 Chain bus 955
Architecture 1275 Channel assignment 131
Asynchronous multiple bus multiprocessor systems 455 Channel pipelining 873
Asynchronous processor simulation 749 Communication overhead 97
Asynchronous transfer mode (ATM) 1159 Communication primitives 1349
ATM 1005 Compressed memory system 1365
Atomic actions 79 Compression algorithm 1365
Atomic commit protocols 809 Computation reordering 551
ATPG 1137 Computational model 49
Computer architecture 23, 1469
Backplane bus 955 Computer vision 259
Bandwidth allocation coefficient 1253 Concurrency control 687, 889
BDD 1137 Content addressable memory (CAM) 1159
BDDs 1321 Context switching 1159
Benchmarks 1013 Coordinated exception handling 79
Benes network 529 Coordination 1419
Binary n-Cube 779 Covert channel 889
Block structured architecture 1469 Crossbar switch 1185
Blocked algorithm 1191 CSMA/CD 1253
Boundary-scan 721 Cube algebra 201
Bridge 105 Cyclic reservation-based MAC protocol 1115
Built-in self-test 181, 721
1383-7621/00/$ - see front matter © 2000 Elsevier Science B.V. All rights reserved.
PII: $1383-7621(00)00044-8
1494 Subject index | Journal of Systems Architecture 46 (2000) 1493-1497
Data driven 675 Fixed priority 991
Data prefetching 1093 Fixed-priority preemptive scheduling 357
Data speculation 1231 Flexible scheduling 49, 305
Dataflow architecture 97 Flexible security 397
Deadlock-free routing 1073 Flow control 1335
Design 483 Folding 105
Design space exploration 1047 Formal verification 1137
Deterministic routing 1103 Forward error recovery 79
DH schemes 1383 FPGA implementation 1275
Diagnosability 519 FPGAs 132
Diagnosis 519 Fractal image compression 1275
Digital signal processor 1403 Frame-sliced signature 655
Dimension-order routing 903 Frequency assignment 131
Direct networks 903 FSM 1137
Directory 903 Full-access unique-path multistage
Disk array architecture 543 interconnection networks (MIN) 529
Disk arrays 1383 Functional partitioning 209
Disk scheduling 379
Disk-cluster database 699
Gbit/s networks 1115
Distributed barrier 411
Graph 779
Distributed computing 145, 627
Graph theory 519
Distributed memories 851
Guarantee algorithms 49
Distributed objects 411
Distributed semaphore 411
Handoff 131
Distributed shared memory 411
Hard real-time 339
Distributed shared-memory multiprocessors 1019
Hardware/software codesign 1263
Distributed systems 809, 1257, 1419
Heterogeneous computing 627
Distributed transaction processing 809
Heterogeneous networks 641
Distributed-memory multiprocessors 675
Heuristics 851
DQDB 601
Hierarchical ring topology 1115
Dual data cache 1451
High speed networks 809
Dual-/multiple-instruction issue 749
High-speed LANs/MANs 1115
Dynamic instruction scheduling 1231
Hypercube 201, 519, 1103
Dynamic reconfiguration 873
Hypergraph 779
Dynamic request rate 39
Hypermesh 779, 1103
Dynamic scheduling 793
Early design stage modeling 1469 Image compression 1275
Embedded memories 181 Imprecise computation 587
Embedded software 1435 Inclusion scheduling 1047
Embedded systems 607, 1335 Incremental testability analysis 209
Error model 607 Indirect conflict 687
Error-cumulative periodic tasks 587 Information retrieval 655
Execution replay 835 Inner product computation 551
Extendable hashing 655 Instruction encoding scheme 1293
Instruction level parallelism 243, 1231 as
Fairness scheduling 1115 Instruction reissue 1231
Fault tolerance 201, 519, 607, 1383 Instruction window design 1231
Fault tolerant 543 Interactive aided design utility ([ADU) 1159
Fault tolerant routing 297 Interconnection 105
Subject index | Journal of Systems Architecture 46 (2000) 1493-1497 1495
Interconnection network 297, 765, 873, 919, Multimedia data 655
1019, 1103, 1349 Multimedia extension 1033
Internet Protocol networks 483 Multimedia standards 601
Isomorphic 951 Multimedia system 1403
Iterated function systems 1275 Multimedia video processor 1403
Multipath switches 1005
Java 79, 145 Multiple context 243
Multiple ring architecture 765
Kernel 1335 Multiple signature comparison 181
Multiprocessor 793
LAN 105 Multiprocessor networks 519
Level scheduling 675 Multiprocessor system 1349
Link failure 519 Multiprocessors 1093
Load balancing 641, 699 Multiprogrammed system 1185
Local autonomy 687 Multistage network 765
Logic synthesis 1321 Multithreaded architecture 1205
Longest executable path 339 Multithreaded video decompres sion 1033
Low power , 551 Multithreading 243
Mandatory and optional subtasks 587 Network management 145
Markovian analysis 455 Network of Workstations 641
Mean value analysis 411 Neurocomputing 429
Measurement 931 Non-stationary signals 513
Memory blockings 455 Non-uniform traffic 39
Memory hierarchy 1365, 1451
Memory hierarchy design 439 Object-oriented design 275
Memory performance evaluation 1365 One-phase commit protocol 809
Memory-processor integration 259 On-line data compression 1365
Memory-testing 181 Operand forwarding 749
Mesh networks 919 Operating systems 379
Message latency 1103 Optional computations 49
Message passing architecture 1257 Output queueing 1005
Message routing 1349 Output traffic distribution 1005
Message-passing 851
Message-Passing Interface (MPI) 675 Parallel and distributed systems 931
Metacomputing 627 Parallel application 1185
Mirroring 543 Parallel computing 919
Mobile agents , 1419 Parallel database systems 699
Mobile computing | Parallel debugging 835
Model-view-controller paradigm 275 Parallel I/O 543
Module selections 1047 Parallel libraries 641
Module utility 1047 Parallel processing 779, 1103, 1185, 1403
Moving Picture Expert Group 2 1043 Parallel signature file 655
MPEG-?2 1033 Parameterized 951
Multicast 919 Parity placement methods 1383
Multicast communication 1073 Performance 483, 851
Multicomputer network 779 Performance analysis 105, 1005, 1103, 1205
Multicomputers 1073, 1103 Performance evaluation 23, 39, 455, 543, 619, 749, 779,
Multidatabase 687 1013, 1185, 1293
Multilevel-secure database correctness criteria 889 Performance prediction 23
1496 Subject index | Journal of Systems Architecture 46 (2000) 1493-1497
Permutation 297 Specification
Petri net 105 Stack resource policy
Pipelined execution 339 Static schedulability analysis
Point-to-point communication bus 955 Statistical simulation
Precedence relations 991 Statistical validation
Priority ceiling protocol 573 Stochastic models
Process visualization development systems 275 STREAMS
Processor-memory integration 973 Stride
Profiling 1263 Stuck-at fault
Program construction 1257 Superscalar processor
Program portability 641 Switching activity
Symbolic model checking
QoS degradation 793 Symbolic techniques
Quality of service (QoS) 1159 Synthesis for testability
Quasi-static scheduling 1435 System architecture
Queueing network model 411 System derivation
Queueing networks 455 System level synthesis
System/process concurrency
Real-time 49, 327, 379, 601, 931 Systolic arrays
Real-time database 397
Real-time scheduling 573, 587
Task scheduling
Real-time system 357, 607, 991, 793, 1403
Task set transformation
Rearrangeable networks 529
Technology mapping
Reconfiguration 951
Technology-dependent synthesis
Register bypassing 749
Temporal locality
Register insertion ring 765
Test pattern generation
Register transfer level 209
Testability analysis
Remote procedure call 835
Threads
Resource constraints 327
Ticket
Resource management system 627
Time-frequency spectrum
Response analysis 721
Time-varying correlogram
Retransmission channel 1253
Trace validation
Router structure 779
Trace-driven simulation
Routers 483
Traffic analysis
Routing 201
Transaction multicasting
Routing algorithm 779
Transaction routing
Transaction scheduling
Scalable multiprocessor implementation 955
Transmission channel
Scan path 721
Tree-based multicast
Scheduling 49, 327, 627, 851, 991
Tree-based techniques
Self-routing 529
Trees
Shared memory multiprocessors 765
Triangular systems
Shortest path 201
Two disk failures
SIMD array 259
Simulation 243, 1013
Utility of service
Simultaneous multithreading 1033
Soft aperiodic task 327
Software synthesis 1435 Validation
Software verification 1435 Value assignment
Spatial locality 1451 Vector processing