Josep Torrellas Professor Computer Science University of Illinois at Urbana Champaign Awards ...

38 Pages·2016·1.36 MB·English

Josep Torrellas
Professor
Computer Science
University of Illinois at Urbana Champaign

Awards and honors and year received (list--no more than *five* items):
• IEEE Computer Society Technical Achievement Award. For ”Pioneering contributions
to shared-memory multiprocessor architectures and thread-level speculation”, June
2015.
• High-Impact Paper Award, International Conference on Computer Design (ICCD).
For ”One of the 5 most cited papers in the first 30 years of ICCD (1983-2012)”,
October 2012.
• ACM Fellow. 2010.
• IEEE Fellow. 2004.
• University of Illinois Willett Faculty Scholar, 2002-2009.

Have you previously been involved in any CRA activities? If so, describe.
• Council Member, The Computing Community Consortium (CCC) of CRA, January
2011-June 2014. Worked in CCC’s Visioning Subcommittee. Received proposals for
visioning workshops, reviewed them, evaluated and discussed them, and acted as a
liaison for one of them.
• Attended the 2015 Leadership in Science Policy Institute Workshop, (LiSPI), CCC,
Washington DC, April 2015.
• Co-organizer of two CCC Visioning Workshops on Advancing Computer Architecture
Research: "Failure is not an Option: Popular Parallel Programming" (February 2010)
and "What Now in ILP Research?” (September 2010). These two workshops lead to
the next one below, which in turn influenced the creation of the Exploiting Parallelism
and Scalability (XPS) solicitation from NSF. Presented the workshop outcome to
CCC, DOE, NSF, AFOSR, and NITRD.
• Co-editor, CCC Visioning white paper: "21st Century Computer Architecture, A
Community White Paper", May 2012. Influenced the creation of XPS.
• Participant in the CRA Visioning workshop: "Revitalizing Computer Architecture
Research", December 2005.
• Member of the Computing Innovation Fellows Selection Committee, CCC and CRA,
2010.

List any other relevant experience and year(s) it occurred (list--no more than
*five* items).
• Director, Illinois-Intel Parallelism Center (I2PC), University of Illinois, September
2011 - September 2013. Center was supported by Intel with $2M. It had 16 faculty. I
organized the "2013 Illinois Symposium on Parallelism: Current State of the Field and
the Future", Urbana, Sept 2013
(http://i2pc.cs.illinois.edu/parworkshop/2013/schedule.html). I lead the preparation of
a book with the research of all the faculty in the Center
(http://iacoma.cs.uiuc.edu/iacoma-papers/Illinois_parallelism_book.pdf).
• Director, Center for Programmable Extreme-Scale Computing, Univ. of Illinois,
January 2011 - pres. Funded by DARPA, DOE, and NSF to focus on architectures
for extreme energy efficiency.
• Professor, Computer Science Department, University of Illinois, August 1992 - pres.
• Leader, University of Illinois OpenSPARC Center of Excellence, September 2007 -
August 2010. Center funded by Sun Microsystems. It included 9 faculty.
• Graduated 35 Ph.D. students, 13 of which are now Professors at leading US
universities, including Cornell University, University of Washington, Georgia Tech,
NCSU, UCSC, University of Rochester, OSU, University of Minnesota, University of
Texas San Antonio, Stony Brook University, University of Southern California, and
University of Pittsburgh.

Research interests: (list only)
• Computer systems architecture
• Parallel computing
• Computer reliability
• Low power design
• Parallel programming models
• Software debugging

Personal Statement
I’ve experience serving the computing research community, and hope to continue doing
so. I've served for three years in the Computing Community Consortium (CCC) Council,
helping shepherd visioning research proposals. I co-organized two workshops on
Advancing Computer Architecture Research, which helped lead to the NSF solicitation
on Exploiting Parallelism and Scalability (XPS). I've been Chair of IEEE Technical
Committee on Computer Architecture (TCCA) for 5 years, where I helped ensure
harmonious conference co-operation. At Illinois, I've been the Director of the Intel Center
for Parallelism, which grouped 16 faculty. I’ve graduated 35 PhDs, 13 of which are now
faculty.

Brief Biography or CV
http://iacoma.cs.uiuc.edu/iacoma-papers/cv_torrellas_july2015.pdf
(Attached)
JosepTorrellas
DepartmentofComputerScience [phone]
UniversityofIllinoisatUrbana-Champaign [phone]FAX
201NorthGoodwinAvenue [email protected]
Urbana,Illinois61801 http://iacoma.cs.uiuc.edu/˜torrellas
July2015
Education
Aug92 Ph.D.inElectricalEngineering,StanfordUniversity.
Dissertation: ”MultiprocessorCacheMemoryPerformance: CharacterizationandOptimization”.
Advisor: JohnHennessy.
Dec87 M.S.inElectricalandComputerEngineering,UniversityofWisconsin-Madison.
Jun86 B.S.inElectricalEngineering,UniversitatPolitecnicadeCatalunya,Spain.
Appointments
Jan11 - pres. Director,CenterforProgrammableExtreme-ScaleComputing,UniversityofIllinoisatUrbana-
Champaign(UIUC).
Sep11 - Sep13 Director,Illinois-IntelParallelismCenter(I2PC),UIUC.
Aug02 - pres. Professor,ComputerScienceDepartment,UIUC.
Aug02 - Aug09 WillettFacultyScholar,ComputerScienceDepartment,UIUC.
Sep07 - Aug10 Leader,UniversityofIllinoisOpenSPARCCenterofExcellence,UIUC.
Feb08 - Aug11 ComputerArchitectureLeader,UniversalParallelComputingResearchCenter(UPCRC),UIUC.
Aug98 - Aug02 AssociateProfessor,ComputerScienceDepartment,UIUC.
May98 - Jan99 ResearchStaffMember,IBMT.J.WatsonResearchCenter,IBMResearch(sabbatical).
Apr93 - pres. DepartmentalAffiliate,ElectricalandComputerEngineeringDepartment,UIUC.
Aug92 - Aug98 AssistantProfessor,ComputerScienceDepartment,UIUC.
Sep92 - Dec96 SeniorComputerSystemsEngineer,CenterforSupercomp. ResearchandDevelop. (CSRD),UIUC.
Honors&Awards
2015 IEEEComputerSocietyTechnicalAchievementAward,June2015. For”Pioneeringcontributions
toshared-memorymultiprocessorarchitecturesandthread-levelspeculation”.
2015 HonorableMentionPaper,IEEEMicroSpecialIssue: 2015Micro’sTopPicksfromComputerArchitecture
Conferences.
2014 DistinguishedPaperAward,InternationalConferenceonProgrammingLanguageDesignandImplementation
(PLDI),June2014.
2014 BestPaperAwardFinalist,InternationalSymposiumonHighPerformanceComputerArchitecture
(HPCA),Feburary2014.
2013 DistinguishedSpeakerAward,IEEEInternationalConferenceonApplicationSpecificSystems,
ArchitecturesandProcessors(ASAP),June2013.
2012 High-ImpactPaperAward,InternationalConferenceonComputerDesign(ICCD),October2012. For”One
ofthe5mostcitedpapersinthefirst30yearsofICCD(1983-2012)”.
2012 JonPostelDistinguishedLecturer,ComputerScienceDepartment,UCLA,November2012.
2010 ACMFellow.
2009 BestPaperAward,42ndInternationalSymposiumonMicroarchitecture(MICRO),December2009.
2009 Paperin2009IEEEMicro’sTopPicksfromComputerArchitectureConferences.
2009 ResearchHighlightpaperinCommunicationsoftheACM(CACM).
2009 BestIdeaAward,WildandCrazyIdeasSession,InternationalConferenceonArchitecturalSupportfor
ProgrammingLanguagesandOperatingSystems(ASPLOS),March2009.
2007 Paperin2007IEEEMicro’sTopPicksfromComputerArchitectureConferences.
2006 BestPaperAward,39thInternationalSymposiumonMicroarchitecture(MICRO),December2006.
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2006 Paperin2006IEEEMicro’sTopPicksfromComputerArchitectureConferences.
2004 Paperin2004IEEEMicro’sTopPicksfromComputerArchitectureConferences.
2004 IEEEFellow.
2003 Paperin2003IEEEMicro’sTopPicksfromComputerArchitectureConferences.
2002-9 WillettFacultyScholar,UIUC.
2001 BestPaperAward,FifthWorkshoponMultithreadedExecution,Architecture,andCompilation.
2000 SeniorXeroxAwardforOutstandingFacultyResearch,UIUC.
1997-00 IBMPartnershipAward.
1997 C.W.GearOutstandingJuniorFacultyAward,UIUC.
1997 JuniorXeroxAwardforOutstandingFacultyResearch,UIUC.
1995,6,8 IntelResearchCouncilAward.
1994-9 YoungInvestigatorAward,NationalScienceFoundation.
1993-6 ResearchInitiationAward,NationalScienceFoundation.
MainProfessionalSocietyService
Apr15 Attendedthe2015LeadershipinSciencePolicyInstituteWorkshop,Computing
CommunityConsortium(CCC),WashingtonDC.
Jan11 - Jun14 CouncilMember,TheComputingCommunityConsortium(CCC),ComputingResearch
Association(CRA).MemberoftheSubcommitteeonVisioningActivities.
June13 Chairandco-editor,”SIGARCH/TCCA’sRecommendedBestPracticesforISCAProgramChairs”.
May12 Co-editor,CCCVisioningwhitepaper: ”21stCenturyComputerArchitecture,ACommunity
WhitePaper”.
Oct10 - Oct19 MemberoftheExecutiveCommittee,TheInstituteofElectricalandElectronicsEngineers(IEEE)
TechnicalCommitteeonComputerArchitecture(TCCA).
Jul05 - Oct10 Chair,IEEETCCA.
Mainactivitiesincluded: organizeandfundover10technicalconferencesyearly,co-ordinate
thefundingandpublicityoftheComputerArchitectureLetters,providefundsforstudentsto
traveltoconferences,serveintheSteeringCommitteesofconferences,andco-locateACMPPoPP
andIEEEHPCAforinterdisciplinaryinteractions.
Feb10 - Sep10 Co-organizeroftwoCCCVisioningWorkshopsonAdvancingComputerArchitectureResearch:
”FailureisnotanOption: PopularParallelProgramming”and”WhatNowinILPResearch?”.
Dec05 ParticipantintheCRAVisioningworkshop: ”RevitalizingComputerArchitectureResearch”.
Jul98 - Jul05 Vice-ChairandMemberoftheAdvisoryBoard,IEEETCCA.
DesignedArchitectures
1. QuickRec: A Hardware Prototype for Recording and Deterministically Replaying Multithreaded Programs in
the Intel Architecture. This prototype has been developed in collaboration with Intel, and is described in the
QuickRecISCA-2013paper: http://iacoma.cs.uiuc.edu/iacoma-papers/isca13 1.pdf.
2. Runnemede: AnChipMultiprocessorforExtreme-ScaleComputing. Thismanycorechiphasbeendesignedin
collaborationwithIntel,andisdescribedintheRunnemedeHPCA-2013paper:http://iacoma.cs.uiuc.edu/iacoma-
papers/hpca13 1.pdf.
DesignedSoftware
1. VARIUS and VARIUS-NTV: A Model of Process Variation. This tool models within-die process variation and
theresultingtimingerrorsinmanycoresatalevelsuitableformicroarchitects. June2007.
http://iacoma.cs.uiuc.edu/varius/index.html.
2. SESC: A Simulator of Superscalar Multiprocessors and Memory Systems with Thread-Level Speculation Sup-
port. SESC is a multiprocessor simulator package with support for thread-level speculation. June 2005.
http://sourceforge.net/projects/sesc.
3. Scal-Tool: PinpointingandQuantifyingScalabilityBottlenecksinDSMMultiprocessors. Scal-Toolisapublic-
domaintoolthatisavailablethroughtheNCSAsoftwarerepository. May1999.
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4. Augmint: A Multiprocessor Simulation Environment for Intel x86 Architectures. Augmint is a multiprocessor
tracingandevaluationpackagethatrunsonIntelx86machines. December1995.
http://iacoma.cs.uiuc.edu/augmint.html.
Publications. Conferences
1. Tanmay Gangwani, Adam Morrison, and Josep Torrellas, ParSync: Breaking Serialization in Lock-Free Mul-
ticore Synchronization, International Conference on Architectural Support for Programming Languages and
OperatingSystems(ASPLOS),April2016.
2. SergiAbadal,EduardAlarcon,AlbertCabellos,andJosepTorrellas,WiSync: AnArchitectureforFastOn-Chip
Synchronization through Wireless-Enabled Global Communication, International Conference on Architectural
SupportforProgrammingLanguagesandOperatingSystems(ASPLOS),April2016.
3. Yuelu Duan, David Koufaty, and Josep Torrellas, SCsafe: Logging Sequential Consistency Violations Contin-
uouslyandPrecisely, InternationalSymposiumonHighPerformanceComputerArchitecture(HPCA),March
2016.
4. Bhargava Gopireddy, Choungki Song, Josep Torrellas, Nam Sung Kim, Aditya Agrawal, and Asit Mishra,
ScalCore: DesigningaCoreforVoltageScalability,InternationalSymposiumonHighPerformanceComputer
Architecture(HPCA),March2016.
5. YueluDuan,NimaHonarmandandJosepTorrellas,AsymmetricMemoryFences:OptimizingBothPerformance
andImplementability,InternationalConferenceonArchitecturalSupportforProgrammingLanguagesandOp-
eratingSystems(ASPLOS),March2015.
6. EhsanTotoni,JosepTorrellas,andLaxmikantV.Kale,UsinganAdaptiveHPCRuntimeSystemtoReconfigure
the Cache Hierarchy, International Conference for High Performance Computing, Networking, Storage and
Analysis(SC),November2014.
7. NimaHonarmandandJosepTorrellas,ReplayDebugging: LeveragingRecordandReplayforProgramDebug-
ging,InternationalSymposiumonComputerArchitecture(ISCA),June2014.
8. Xuehai Qian, Benjamin Sahelices, and Josep Torrellas, OmniOrder: Directory-Based Coherence for Conflict
Serialization,InternationalSymposiumonComputerArchitecture(ISCA),June2014.
9. Wonsun Ahn, Jiho Choi, Thomas Shull, Maria Garzaran, and Josep Torrellas, Improving JavaScript Perfor-
mance Through Predictable Type Specialization International Conference on Programming Language Design
andImplementation(PLDI),June2014. DistinguishedPaperAward.
10. NimaHonarmandandJosepTorrellas,RelaxReplay: RecordandReplayforRelaxed-ConsistencyMultiproces-
sors, International Conference on Architectural Support for Programming Languages and Operating Systems
(ASPLOS),March2014.
11. JosepTorrellas,Extreme-ScaleComputerArchitecture:EnergyEfficiencyfromtheGroundUp,DesignAutoma-
tionandTestinEurope(DATE),March2014.
12. AdityaAgrawal, AminAnsari, andJosepTorrellas, Mosaic: ExploitingtheSpatialLocalityofProcessVaria-
tion to Reduce Refresh Energy in On-Chip eDRAM Modules, International Symposium on High Performance
ComputerArchitecture(HPCA),February2014.
13. Amin Ansari, Asit Mishra, Jianping Xu, and Josep Torrellas, Tangle: Route-Oriented Dynamic Voltage Mini-
mizationforVariation-Afflicted,Energy-EfficientOn-ChipNetworks,InternationalSymposiumonHighPerfor-
manceComputerArchitecture(HPCA),February2014.
14. Shanxiang Qi, Abdullah Muzahid, Wonsun Ahn, and Josep Torrellas, Dynamically Detecting and Tolerating
IF-Condition Data Races, International Symposium on High Performance Computer Architecture (HPCA),
February2014.
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15. XuehaiQian,BenjaminSahelices,JosepTorrellas,andDepeiQian,BulkCommit: ScalableandFastCommitof
AtomicBlocksinaLazyMultiprocessorEnvironment,InternationalSymposiumonMicroarchitecture(MICRO),
December2013.
16. Gilles Pokam, Klaus Danne, Cristiano Pereira, Rolf Kassa, Tim Kranich, Shiliang Hu, and Justin Gottschlich
(Intel),andNimaHonarmand,NathanDautenhahn,SamKingandJosepTorrellas(UIUC),QuickRec:Prototyp-
inganIntelArchitectureExtensionforRecordandReplayofMultithreadedPrograms,InternationalSymposium
onComputerArchitecture(ISCA),June2013.
17. YueluDuan,AbdullahMuzahid,andJosepTorrellas,WeeFence: TowardMakingFencesFreeinTSO,Interna-
tionalSymposiumonComputerArchitecture(ISCA),June2013.
18. Wonsun Ahn, Yuelu Duan and Josep Torrellas, DeAliaser: Alias Speculation Using Atomic Region Support,
InternationalConferenceonArchitecturalSupportforProgrammingLanguagesandOperatingSystems(ASP-
LOS),March2013.
19. byNimaHonarmand,NathanDautenhahn,JosepTorrellas,SamuelKing,GillesPokamandCristianoPereira,
Cyrus: UnintrusiveApplication-LevelRecord-ReplayforReplayParallelism, InternationalConferenceonAr-
chitecturalSupportforProgrammingLanguagesandOperatingSystems(ASPLOS),March2013.
20. Xuehai Qian, Benjamin Sahelices, Josep Torrellas and Depei Qian, Volition: Scalable and Precise Sequen-
tialConsistencyViolationDetection,InternationalConferenceonArchitecturalSupportforProgrammingLan-
guagesandOperatingSystems(ASPLOS),March2013.
21. Nicholas P. Carter, Aditya Agrawal, Shekhar Borkar, Romain Cledat, Howard David, Dave Dunning, Joshua
Fryman, Ivan Ganev, Roger A. Golliver, Rob Knauerhase, Richard Lethin, Benoit Meister, Asit K. Mishra,
WilfredR.Pinfold,JustinTeller,JosepTorrellas,NicolasVasilache,GaneshVenkatesh,andJianpingXu,Run-
nemede: AnArchitectureforUbiquitousHigh-PerformanceComputing,InternationalSymposiumonHighPer-
formanceComputerArchitecture(HPCA),February2013.
22. Ulya R. Karpuzcu, Abhishek Sinkar, Nam Sung Kim, and Josep Torrellas, EnergySmart: Toward Energy-
EfficientManycoresforNear-ThresholdComputing,InternationalSymposiumonHighPerformanceComputer
Architecture(HPCA),February2013.
23. AdityaAgrawal,PrabhatJain,AminAnsariandJosepTorrellas,Refrint: IntelligentRefreshtoMinimizePower
inOn-ChipMultiprocessorCacheHierarchies, InternationalSymposiumonHighPerformanceComputerAr-
chitecture(HPCA),February2013.
24. Amin Ansari, Shuguang Feng, Shantanu Gupta, Josep Torrellas, and Scott Mahlke, Illusionist: Transforming
LightweightCoresintoAggressiveCoresonDemand,InternationalSymposiumonHighPerformanceComputer
Architecture(HPCA),February2013.
25. AbdullahMuzahid,ShanxiangQiandJosepTorrellas,Vulcan:HardwareSupportforDetectingSequentialCon-
sistencyViolationsDynamically,InternationalSymposiumonMicroarchitecture(MICRO),December2012.
26. Josep Torrellas, FlexRAM: Toward an Advanced Intelligent Memory System. A Retrospective Paper, Interna-
tionalConferenceonComputerDesign(ICCD),September2012.
27. UlyaR.Karpuzcu,KrishnaB.Kolluru,NamSungKimandJosepTorrellas,VARIUS-NTV:AMicroarchitectural
Model to Capture the Increased Sensitivity of Manycores to Process Variations at Near-Threshold Voltages,
InternationalConferenceonDependableSystemsandNetworks(DSN),June2012. AcceptanceRate: 17%.
28. Ehsan Totoni, Babak Behzad, Swapnil Ghike and Josep Torrellas, Comparing the Power and Performance of
Intel’sSCCtoState-of-the-ArtCPUsandGPUs,InternationalSymposiumonPerformanceAnalysisofSystems
andSoftware(ISPASS),April2012.
29. XuehaiQian,BenjaminSahelicesandJosepTorrellas,BulkSMT:DesigningSMTProcessorsforAtomic-Block
Execution,InternationalSymposiumonHighPerfomanceComputerArchitecture(HPCA),February2012.
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30. Shanxiang Qi, Norimasa Otsuki, Lois Orosa, Abdullah Muzahid, and Josep Torrellas, Pacman: Tolerating
AsymmetricDataRaceswithUnintrusiveHardware,InternationalSymposiumonHighPerfomanceComputer
Architecture(HPCA),February2012.
31. YueluDuan, XingZhou, WonsunAhn, andJosepTorrellas, BulkCompactor: OptimizedDeterministicExecu-
tion via Conflict-Aware Commit of Atomic Blocks, International Symposium on High Perfomance Computer
Architecture(HPCA),February2012.
32. RishiAgarwalandJosepTorrellas,FlexBulk: IntelligentlyFormingAtomicBlocksinBlocked-ExecutionMulti-
processorstoMinimizeSquashes,InternationalSymposiumonComputerArchitecture(ISCA),June2011.
33. RishiAgarwal,PranavGarg,andJosepTorrellas,Rebound: ScalableCheckpointingforCoherentSharedMem-
ory,InternationalSymposiumonComputerArchitecture(ISCA),June2011.
34. XuehaiQian,WonsunAhn,andJosepTorrellas,ScalableBulk: ScalableCacheCoherenceforAtomicBlocksin
aLazyEnvironment, InternationalSymposiumonMicroarchitecture(MICRO),December2010. (17%accep-
tancerate).
35. AbdullahMuzahid,NorimasaOtsuki,andJosepTorrellas,AtomTracker: AComprehensiveApproachtoAtomic
RegionInferenceandViolationDetection,InternationalSymposiumonMicroarchitecture(MICRO),December
2010. (17%acceptancerate).
36. AdrianNistor, DarkoMarinov, andJosepTorrellas, InstantCheck: CheckingtheDeterminismofParallelPro-
grams Using On-the-fly Incremental Hashing, International Symposium on Microarchitecture (MICRO), De-
cember2010. (17%acceptancerate).
37. Brian Greskamp, Ulya R. Karpuzcu, and Josep Torrellas, LeadOut: Composing Low-Overhead Frequency-
EnhancingTechniquesforSingle-ThreadPerformanceinConfigurableMulticores,InternationalSymposiumon
High-PerformanceComputerArchitecture(HPCA),January2010.
38. Wonsun Ahn, Shanxiang Qi, Jae-Woo Lee, Marios Nicolaides, Xing Fang, Josep Torrellas, David Wong, and
SamuelMidkiff,BulkCompiler: High-PerformanceSequentialConsistencythroughCooperativeCompilerand
HardwareSupport,InternationalSymposiumonMicroarchitecture(MICRO),December2009.
39. UlyaR.Karpuzcu,BrianGreskampandJosepTorrellas,TheBubbleWrapMany-Core: PoppingCoresforSe-
quentialAcceleration,InternationalSymposiumonMicroarchitecture(MICRO),December2009. BestPaper
Award.
40. Adrian Nistor, Darko Marinov, and Josep Torrellas, Light64: Lightweight Hardware Support for Race Detec-
tionduringSystematicTestingofParallelPrograms,InternationalSymposiumonMicroarchitecture(MICRO),
December2009.
41. Abdullah Muzahid, Dario Suarez, Shanxiang Qi, and Josep Torrellas, SigRace: Signature-Based Data Race
Detection,InternationalSymposiumonComputerArchitecture(ISCA),June2009.
42. Pablo Montesinos, Matthew Hicks, Samuel T. King, and Josep Torrellas, Capo: A Software-Hardware Inter-
faceforPracticalDeterministicMultiprocessorReplay,InternationalConferenceonArchitecturalSupportfor
ProgrammingLanguagesandOperatingSystems(ASPLOS),March2009.
43. Brian Greskamp, R. Ulya Karpuzcu, and Josep Torrellas, BubbleWrap: Popping CMP Cores for Sequential
Acceleration,WildandCrazyIdeasSession,atInternationalConferenceonArchitecturalSupportforProgram-
mingLanguagesandOperatingSystems(ASPLOS),March2009. BestIdeaAward.
44. BrianGreskamp,LuWan,UlyaR.Karpuzcu,JeffreyJ.Cook,JosepTorrellas,DemingChen,andCraigZilles,
BlueShift: Designing Processors for Timing Speculation from the Ground Up, International Symposium on
High-PerformanceComputerArchitecture(HPCA),February2009.
45. Abhishek Tiwari and Josep Torrellas, Facelift: Hiding and Slowing Down Aging in Multicores, International
SymposiumonMicroarchitecture(MICRO),November2008.
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46. Smruti Sarangi, Brian Greskamp, Abhishek Tiwari, and Josep Torrellas, EVAL: Utilizing Processors with
Variation-InducedTimingErrors,InternationalSymposiumonMicroarchitecture(MICRO),November2008.
47. Pablo Montesinos, Luis Ceze, and Josep Torrellas, DeLorean: Recording and Deterministically Replaying
Shared-MemoryMultiprocessorExecutionEfficiently,InternationalSymposiumonComputerArchitecture(ISCA),
June2008.
48. Radu Teodorescu and Josep Torrellas, Variation-Aware Application Scheduling and Power Management for
ChipMultiprocessors,InternationalSymposiumonComputerArchitecture(ISCA),June2008.
49. James Tuck, Wonsun Ahn, Luis Ceze, and Josep Torrellas, SoftSig: Software-Exposed Hardware Signatures
forCodeAnalysisandOptimization,InternationalConferenceonArchitecturalSupportforProgrammingLan-
guagesandOperatingSystems(ASPLOS),March2008.
50. Karin Strauss, Xiaowei Shen, and Josep Torrellas, Unconstrained Snoop Request Delivery in Embedded-Ring
Multiprocessors,InternationalSymposiumonMicroarchitecture(MICRO),December2007.
51. RaduTeodorescu,JunNakano,AbhishekTiwariandJosepTorrellas,MitigatingParameterVariationwithDy-
namicFine-GrainBodyBiasing,InternationalSymposiumonMicroarchitecture(MICRO),December2007.
52. James Tuck, Wei Liu, and Josep Torrellas, CAP: Criticality Analysis for Power-Efficient Speculative Multi-
threading,InternationalConferenceonComputerDesign(ICCD),October2007.
53. CyrusBazeghi,FranciscoJ.Mesa-Martinez,BrianGreskamp,JosepTorrellas,andJoseRenau,EstimatingDe-
signTimeforSystemCircuits,InternationalConferenceonVeryLargeScaleIntegration(VLSI-SoC),October
2007.
54. Brian Greskamp and Josep Torrellas, Paceline: Improving Single-Thread Performance in Nanoscale CMPs
through Core Overclocking, International Conference on Parallel Architectures and Compilation Techniques
(PACT),September2007.
55. Luis Ceze, James M. Tuck, Pablo Montesinos, and Josep Torrellas, BulkSC: Bulk Enforcement of Sequential
Consistency,InternationalSymposiumonComputerArchitecture(ISCA),June2007.
56. Abhishek Tiwari, Smruti Sarangi, and Josep Torrellas, ReCycle: Pipeline Adaptation to Tolerate Parameter
Variation,InternationalSymposiumonComputerArchitecture(ISCA),June2007.
57. PabloMontesinos, WeiLiu, andJosepTorrellas, UsingRegisterLifetimePredictionstoProtectRegisterFiles
AgainstSoftErrors,InternationalConferenceonDependableSystemsandNetworks(DSN),June2007.
58. Brian Greskamp, Smruti Sarangi, and Josep Torrellas, Threshold Voltage Variation Effects on Aging-Related
HardFailureRates, InternationalSymposiumonCircuitsandSystems(ISCAS),SpecialSession: CircuitDe-
signinthePresenceofDeviceVariability,May2007.
59. SmrutiSarangi,BrianGreskamp,andJosepTorrellas,AModelforTimingErrorsinProcessorswithParameter
Variation,InternationalSymposiumonQualityElectronicDesign(ISQED),March2007.
60. LuisCeze,PabloMontesinos,ChristophvonPraun,andJosepTorrellas,Colorama: ArchitecturalSupportfor
Data-CentricSynchronization,InternationalSymposiumonHigh-PerformanceComputerArchitecture(HPCA),
February2007.
61. SmrutiR.Sarangi,AbhishekTiwari,andJosepTorrellas,Phoenix: DetectingandRecoveringfromPermanent
Processor Design Bugs with Programmable Hardware, International Symposium on Microarchitecture (MI-
CRO),December2006. BestPaperAward.
62. JamesTuck,LuisCeze,andJosepTorrellas,ScalableCacheMissHandlingforHighMemory-LevelParallelism,
InternationalSymposiumonMicroarchitecture(MICRO),December2006.
63. Shan Lu, Pin Zhou, Wei Liu, Yuanyuan Zhou, and Josep Torrellas, PathExpander: Architectural Support for
IncreasingthePathCoverageofDynamicBugDetection,InternationalSymposiumonMicroarchitecture(MI-
CRO),December2006.
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64. PabloMontesinos,WeiLiu,andJosepTorrellas,Shield: Cost-EffectiveSoft-ErrorProtectionforRegisterFiles,
ThirdIBMTJWatsonConferenceonInteractionbetweenArchitecture,CircuitsandCompilers(P=AC2),Oc-
tober2006.
65. L.Ceze,J.Tuck,C.Cascaval,andJ.Torrellas,BulkDisambiguationofSpeculativeThreadsinMultiprocessors,
InternationalSymposiumonComputerArchitecture(ISCA),June2006.
66. K. Strauss, X. Shen, and J. Torrellas, Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in
Embedded-RingMultiprocessors,InternationalSymposiumonComputerArchitecture(ISCA),June2006.
67. S.Sarangi,B.Greskamp,andJ.Torrellas,CADRE:Cycle-AccurateDeterministicReplayforHardwareDebug-
ging,InternationalConferenceonDependableSystemsandNetworks(DSN),June2006.
68. W.Liu,J.Tuck,L.Ceze,W.Ahn,K.Strauss,J.RenauandJ.Torrellas,POSH:ATLSCompilerthatExploits
ProgramStructure,SymposiumonPrinciplesandPracticeofParallelProgramming(PPoPP),March2006.
69. J. Nakano, P. Montesinos, K. Gharachorloo, and J. Torrellas, ReViveI/O: Efficient Handling of I/O in Highly-
Available Rollback-Recovery Servers, International Symposium on High-Performance Computer Architecture
(HPCA),February2006.
70. S. Sarangi, W. Liu, J. Torrellas, and Y. Zhou, ReSlice: Selective Re-Execution of Long-Retired Misspeculated
InstructionsUsingForwardSlicing,InternationalSymposiumonMicroarchitecture(MICRO),November2005.
71. W.Liu,J.Tuck,L.Ceze,K.Strauss,J.Renau,andJ.Torrellas,POSH:AProfiler-EnhancedTLSCompilerthat
LeveragesProgramStructure,WatsonConferenceonInteractionbetweenArchitecture,Circuits,andCompilers
(P=AC2),September2005.
72. M. Wei, M. Snir, J. Torrellas, and R. B. Tremaine, A Near-Memory Processor for Vector, Streaming and Bit
Manipulation Workloads, Watson Conference on Interaction between Architecture, Circuits, and Compilers
(P=AC2),September2005.
73. J.Renau,K.Strauss,L.Ceze,W.Liu,S.Sarangi,J.Tuck,andJ.Torrellas,Thread-LevelSpeculationonaCMP
CanBeEnergyEfficient,InternationalConferenceonSupercomputing(ICS),June2005.
74. J.Renau,J.Tuck,W.Liu,L.Ceze,K.Strauss,andJ.Torrellas,TaskingwithOut-of-OrderSpawninTLSChip
Multiprocessors:MicroarchitectureandCompilation,InternationalConferenceonSupercomputing(ICS),June
2005.
75. R.TeodorescuandJ. Torrellas, PrototypingArchitecturalSupportforProgramRollback Using FPGAs, Sym-
posiumonField-ProgrammableCustomComputingMachines(FCCM),April2005.
76. P.Zhou,W.Liu,F.Long,S.Lu,F.Qin,Y.Zhou,S.MidkiffandJ.Torrellas,AccMon: AutomaticallyDetecting
Memory-RelatedBugsviaProgramCounter-BasedInvariants,InternationalSymposiumonMicroarchitecture
(MICRO),December2004.
77. P. Zhou, F. Qin, W. Liu, Y.Zhou, and J. Torrellas, iWatcher: Efficient Architectural Support for Software De-
bugging,InternationalSymposiumonComputerArchitecture(ISCA),June2004.
78. A.NguyenandJ.Torrellas, DesignTrade-offsinHigh-ThroughputCoherenceControllers, InternationalCon-
ference on Parallel Architectures and Compilation Techniques (PACT), September 2003. Acceptance Rate:
17%.
79. M. Garzaran, M. Prvulovic, J. Llaberia, V. Vinals, L. Rauchwerger, and J. Torrellas, Using Software Logging
toSupportMulti-VersionBufferinginThread-LevelSpeculation,InternationalConferenceonParallelArchitec-
turesandCompilationTechniques(PACT),September2003. AcceptanceRate: 17%.
80. B. Fraguela, J. Renau, P. Feautrier, D. Padua, and Josep Torrellas, Programming the FlexRAM Parallel Intel-
ligentMemorySystem,InternationalSymposiumonPrinciplesandPracticeofParallelProgramming(PPoPP),
June2003.
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81. M.PrvulovicandJ.Torrellas,ReEnact:UsingThread-LevelSpeculationtoDebugDataRacesinMultithreaded
Codes,InternationalSymposiumonComputerArchitecture(ISCA),June2003.
82. M. Huang, J. Renau, and J. Torrellas, Positional Adaptation of Processors: Application to Energy Reduction,
InternationalSymposiumonComputerArchitecture(ISCA),June2003.
83. M. Garzaran, M. Prvulovic, J. Llaberia, V. Vinals, L. Rauchwerger, and J. Torrellas, Tradeoffs in Buffering
MemoryStateforThread-LevelSpeculationinMultiprocessors,InternationalSymposiumonHigh-Performance
ComputerArchitecture(HPCA),February2003.
84. J. Martinez, J. Renau, M. Huang, M. Prvulovic, and J. Torrellas, Cherry: Checkpointed Early Resource Re-
cyclinginOut-of-orderMicroprocessors,InternationalSymposiumonMicroarchitecture(MICRO),November
2002.
85. J.MartinezandJ.Torrellas,SpeculativeSynchronization:ApplyingThread-LevelSpeculationtoParallelAppli-
cations,InternationalConferenceonArchitecturalSupportforProgrammingLanguagesandOperatingSystems
(ASPLOS),October2002. AcceptanceRate: 18%.
86. M.Huang,J.Renau,andJ.Torrellas,Energy-EfficientHybridWakeupLogic,InternationalSymposiumonLow
PowerElectronicsandDesign(ISLPED),August2002. AcceptanceRate: 24%.
87. M.Prvulovic, Z.Zhang, andJ.Torrellas. ReVive: Cost-EffectiveArchitecturalSupportforRollbackRecovery
in Shared-Memory Multiprocessors, International Symposium on Computer Architecture (ISCA), May 2002.
AcceptanceRate: 15%.
88. Y.Solihin,J.Lee,andJ.Torrellas,UsingaUser-LevelMemoryThreadforCorrelationPrefetching,International
SymposiumonComputerArchitecture(ISCA),May2002. AcceptanceRate: 15%.
89. M.CintraandJ.Torrellas,EliminatingSquashesThroughLearningCross-ThreadViolationsinSpeculativePar-
allelizationforMultiprocessors,EigthInternationalSymposiumonHigh-PerformanceComputerArchitecture
(HPCA),February2002.
90. M. Garzaran, M. Prvulovic, A. Jula, H. Yu, Y. Zhang, L. Rauchwerger, and J. Torrellas, Architectural Sup-
portforParallelReductionsinScalableShared-MemoryMultiprocessors,InternationalConferenceonParallel
ArchitecturesandCompilationTechniques(PACT),Barcelona,September2001.
91. M. Huang, J. Renau, S.-M. Yoo, and J. Torrellas, L1 Data Cache Decomposition for Energy Efficiency, Inter-
national Symposium on Low Power Electronics and Design (ISLPED), pp. 10-15, August 2001. Acceptance
Rate: 24%.
92. M. Prvulovic, M. J. Garzaran, L. Rauchwerger, and J. Torrellas. Removing Architectural Bottlenecks to the
ScalabilityofSpeculativeParallelization,InternationalSymposiumonComputerArchitecture(ISCA),pp.204-
215,June2001. AcceptanceRate: 14%.
93. J.Lee,Y.Solihin,andJ.Torrellas,AutomaticallyMappingCodeonanIntelligentMemoryArchitecture,Inter-
nationalSymposiumonHigh-PerformanceComputerArchitecture(HPCA),pp121-132,January2001. Accep-
tanceRate: 23%.
94. M. Huang, J. Renau, S.-M. Yoo, and J. Torrellas, A Framework for Dynamic Energy Efficiency and Temper-
ature Management, International Symposium on Microarchitecture (MICRO), pp 202-213, December 2000.
AcceptanceRate: 28%.
95. Q.Cao,J.Torrellas,andH.-V.Jagadish,UnifiedFine-GranularityBufferingofIndexandData: Approachand
Implementation,InternationalConferenceonComputerDesign(ICCD),September2000.
96. M.Cintra,J.MartinezandJ.Torrellas,ArchitecturalSupportforScalableSpeculativeParallelizationinShared-
Memory Multiprocessors, International Symposium on Computer Architecture (ISCA), pp 13-24, June 2000.
AcceptanceRate: 17%.
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