Integrating Instruction Set Simulator into a System Level Design

85 Pages·2013·2.01 MB·English

by  Akash Agarwal

Integrating Instruction Set Simulator into a System Level Design
Environment
AThesisPresented
by
AkashAgarwal
to
TheDepartmentofElectricalandComputerEngineering
inpartialfulfillmentoftherequirements
forthedegreeof
MasterofScience
in
ElectricalandComputerEngineering
NortheasternUniversity
Boston,Massachusetts
February2013
NORTHEASTERN UNIVERSITY
GraduateSchoolofEngineering
ThesisTitle: IntegratingInstructionSetSimulatorintoaSystemLevelDesignEnvironment.
Author: AkashAgarwal.
Department: ElectricalandComputerEngineering.
ApprovedforThesisRequirementsoftheMasterofScienceDegree
ThesisAdvisor: Dr. GunarSchirner Date
ThesisReader: Dr. DavidKaeli Date
ThesisReader: Dr. NinfangMi Date
DepartmentChair: Dr. AliAbur Date
Dean: Dr. SaraWadia-Fascetti Date
Tomyfamily.
ii
Contents
ListofFigures v
ListofTables vii
ListofAcronyms viii
Acknowledgments ix
AbstractoftheThesis x
1 Introduction 1
1.1 EmbeddedSystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 GrowthandChallenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 SystemLevelDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 VirtualPlatform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 ProblemDefinition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Background 10
2.1 SystemonChipEnvironment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 DiscreteEventSimulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 InstructionSetSimulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 BlackfinFamilyProcessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 RelatedWork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 ISSIntegrationGuidelines 18
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 ISSIntegration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1 ExecutionModelIntegration . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2 TimeSynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.3 BusSystemIntegration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.4 InterruptPropagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.5 SupportDebuggingEnvironmentonISS . . . . . . . . . . . . . . . . . . 37
3.2.6 SupportProfilingExecutiononISS . . . . . . . . . . . . . . . . . . . . . 37
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4 IntegratingBlackfinGDBISS 39
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2 GDBISSIntegration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2.1 ExecutionModelIntegration . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.2 TimeSynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.3 BusSystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.4 InterruptPropagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2.5 SupportDebuggingEnvironmentonGDBISS . . . . . . . . . . . . . . . 47
5 ExperimentalResults 49
5.1 AccuracyofBF527GDBISS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.1.2 ExperimentalSetup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.1.3 AnalysisandResults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.2 EffectofQuantum-basedTimeSynchronizationonInterruptLatency . . . . . . . . 53
5.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2.2 ExperimentalSetup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2.3 ImpactofQuantumSynchronizationontoQuantumLatencyandResponse
Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2.4 Impact of Variable Quantum Length on Total Simulation Time and Quan-
tumLatency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3 DesignSpaceExploration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.1 AlgorithmUnderTest . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.2 TestResults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6 Conclusion 63
Bibliography 65
A TestCases 69
A.1 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
A.1.1 ExecutionandTimeSynchronizationTestCase . . . . . . . . . . . . . . . 70
A.1.2 BusReadandWriteTestCase . . . . . . . . . . . . . . . . . . . . . . . . 70
A.2 ArchitecturalMapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
A.2.1 ExecutionandTimesynchronizationTestCase . . . . . . . . . . . . . . . 71
A.2.2 BusReadandWriteTestCase . . . . . . . . . . . . . . . . . . . . . . . . 72
iv
List of Figures
1.1 EmbeddedSystemOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 SystemOnChipOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Productivitygap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 ITRSReport2011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 AbstractionLevels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6 SoCDesignFlow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.7 SimplifiedVirtualPlatform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 SystemOnChipEnvironment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 ISSSoftwareFlow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 CoreISS:ISSwithonlyCoresupport . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 SystemISS:ISSwithcore&andotherperipheralsupport. . . . . . . . . . . . . . 15
2.5 ADSP-BF527blockdiagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 SoCBlockDiagramshowingonlytheEssentialComponents . . . . . . . . . . . . 20
3.2 SimplifiedVPblockDiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 ISSSoftwareMainloop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 ISSSoftwareMainLoopModified . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5 Sample Code Execution Sequence on SoC showing 3 different types of possible
CodeSequenceonISS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 UpdateofVPtimeduetoExecutionofComponentModelsinQuantum . . . . . . 25
3.7 TimeSynchronizationatQuantumExpiration . . . . . . . . . . . . . . . . . . . . 25
3.8 ExectionSequenceoftheSpecificationtillBusAccess . . . . . . . . . . . . . . . 26
3.9 TimeSynchronizationatBusAccess . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10 ExecutionSequenceatInterruptPropagation . . . . . . . . . . . . . . . . . . . . . 28
3.11 TimeSynchronizationatInterrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.12 CoreISSVP,depictingtheBusChannelIntegration . . . . . . . . . . . . . . . . . 32
3.13 SystemISSdepictingtheBusChannelIntegration . . . . . . . . . . . . . . . . . . 32
3.14 CoreISSVPdepictingtheInterruptIntegration . . . . . . . . . . . . . . . . . . . 35
3.15 SystemISSVPdepictingtheInterruptIntegration . . . . . . . . . . . . . . . . . . 36
4.1 SimplifiedBlackfinGDBISSblockdiagrm . . . . . . . . . . . . . . . . . . . . . 40
4.2 Blackfin52xMemoryMap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3 BFINbasedVPdepictingtheBusSystemIntegration . . . . . . . . . . . . . . . . 43
v
4.4 BFINbasedVPdepictingtheInterruptConnections . . . . . . . . . . . . . . . . . 44
4.5 Interrupt Prorogation Sequence Inside the VP(When quantum lss then width of in-
terrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6 HighlevelCodeSequenceExecutiononHardwareandISS . . . . . . . . . . . . . 46
4.7 ExecutionSequenceofHardwareandISS . . . . . . . . . . . . . . . . . . . . . . 46
4.8 HighlevelCodeSequenceExecutiononHardware,LatchandISS . . . . . . . . . 47
4.9 ExecutionSequenceofHardware,ISSandLatchshowingInterruptsbeingcaptured 47
4.10 InterruptIntegrationwithAdditionalLatch . . . . . . . . . . . . . . . . . . . . . 48
5.1 GraphforPercentageInaccuracyofISS . . . . . . . . . . . . . . . . . . . . . . . 51
5.2 ExperminentalSetuptomeausreInterruptLatency . . . . . . . . . . . . . . . . . 54
5.3 SimulationLatencyforISS@Quantum10000withdifferentworkload . . . . . . 56
5.4 ResponseTimeforISS@Quantum10000withdifferentworkload . . . . . . . . 56
5.5 Quantum latency and Simulation time for different quantum length for LOAD ap-
plication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.6 Quantum latency and Simulation time for different quantum length for a BUSAC-
CESSapplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.7 TopLevelofMP3SpeCSpecificationModel . . . . . . . . . . . . . . . . . . . . 61
A.1 SpecificationofExecutionandTimeSynchronizationTestCase . . . . . . . . . . 70
A.2 SpecificationofBusRead/WriteTestCase . . . . . . . . . . . . . . . . . . . . . . 70
A.3 ProcessorbasedSynchronizationTestCaseCase . . . . . . . . . . . . . . . . . . 71
A.4 HWBasedSynchronizationwithPollingBasedSynchronization . . . . . . . . . . 71
A.5 HWbasedSynchronizationwithInterruptsbasedSynchronization . . . . . . . . . 72
A.6 BusWriteTest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
A.7 BusReadwithPollingTest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
A.8 BusReadwithInterruptTest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
vi
List of Tables
5.1 CoreClockCyclesonBF-527HWandISSforBenchmark . . . . . . . . . . . . . 51
5.2 MemoryStallnumbersforbenchmark . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3 QuantumLatencyandSimulationTimeforLOADapplication . . . . . . . . . . . 58
5.4 Table showing Quantum Latency variation over quantum length for BUSACCESS
application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.5 MP3decoderexpolorationonARMandBFINbasedVP . . . . . . . . . . . . . . 62
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List of Acronyms
ESL ElectronicSystemLevelAElectronicSystemLeveldesignisanemergingelectronicdesign
andverificationapproachwhichfocussesonhigherabstractionlevelfordesign
GPIO GeneralPurposeInputandOutputAGeneralPurposeInputandOutputisagenericpinina
chip,whosebehaviourandfunctionalityiscontrolledbytheuseratruntime
HDS HardwareDependentSoftwareHardwareDependentSoftwareisthepartoftheoperating
system,comprisingmainlyofdevicedriversandbootcode. Itservesthefunctionalityof
hardwareinitialization
IC IntegratedCircuitIntegratedCircuitisasetofelectroniccircuitononesmallsemiconductor
material
ISS InstructionSetSimulatorAnInstructionSetSimulatorisansoftwarethatsimulatesthetarget
processor.
PIC ProgrammableInterruptControllerProgrammableInterruptControllerisadevicethatisused
tocombineseveralsourcesofinterruptontooneormoreCPUlines.
RTL RegisterTransferLevelRegistertransferLevelisadesignabstractionwhichmodels
synchronousdigitalcircuitintermofflowofdigitalsignalbetweenhardwareregisters
SoC SystemonChipAIntegratedCircuitcomponentwhichintegratesdifferentcomponentsina
electronicdeviceinasinglechip
SLDL SystemLevelDesignLanguagesSystemLevelDesignLanguagesisusedtoaidthedesign
anddevelopspecificationofdigitalembeddedsystem
SCE SystemonChipEnvironmentSystemonChipEnvironmentisaElectronicSystemLevel
DesignTooldevelopedatUniversityofCalifornia,Irvine.
TLM TransactionLevelModelling. TransactionLevelmodellingisanhighlevelapproachof
modellingcommunicationamongmodulesassetoftransactions
VP VirtualPlatformVirtualPlatformisasoftwareimplementedabstractionofthehardware
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Acknowledgments
Iwishtothankmyfamily,friendsandaspecialthankstoMikeFrishengerforhisguidance
anddevelopingBlackfinISSunderGNU,RohanKangarkalarforhisworkonRTOSintegration,and
ProfGunarSchirnerforhiscontinuanceguidanceandsupport.
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