Integrated Interconnect Technologies for 3D Nanoelectronic Systems

551 Pages·2008·12.812 MB·English

by  Muhannad S. Bakir, James D. Meindl

Integrated Interconnect Technologies
for 3D Nanoelectronic Systems
For a list of recent titles in the Artech House Integrated Microsystems Series,
please turn to the back of this book
Integrated Interconnect Technologies
for 3D Nanoelectronic Systems
Muhannad S. Bakir
James D. Meindl
Editors
artechhouse.com
Library of Congress Cataloging-in-Publication Data
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A catalogue record for this book is available from the British Library.
ISBN-13: 978-1-59693-246-3
Cover design by Igor Valdman
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10 9 8 7 6 5 4 3 2 1
This book is dedicated to my mom and dad,
and brothers, Tariq and Basil
and for the never ending support and inspiration
M.S.B.

Contents
Foreword xvii
Preface xix
CHAPTER 1
Revolutionary Silicon Ancillary Technologies for the Next Era of
Gigascale Integration 1
1.1 Introduction 1
1.2 The Role of Innovation in Sustaining Moore’s Law 2
1.3 Silicon Technology: The Three Eras 5
1.3.1 First Era: Transistor Centricity (1960s Through 1980s) 5
1.3.2 Second Era: On-Chip Interconnect Centricity (1990s) 6
1.3.3 Third Era: Chip I/O Centricity (2000s) 8
1.4 Need for Disruptive Silicon Ancillary Technologies: Third Era of
1.4 Silicon Technology 16
1.5 Conclusion 17
References 19
CHAPTER 2
Chip-Package Interaction and Reliability Impact on Cu/Low-k Interconnects 23
2.1 Introduction 23
2.2 Experimental Techniques 25
2.2.1 Thermomechanical Deformation of Organic Flip-Chip Package 25
2.2.2 Measurement of Interfacial Fracture Toughness 28
2.3 Mechanics of Cohesive and Interfacial Fracture in Thin Films 32
2.3.1 Channel Cracking 32
2.3.2 Interfacial Delamination 34
2.4 Modeling of Chip-Packaging Interactions 38
2.4.1 Multilevel Submodeling Technique 39
2.4.2 Modified Virtual Crack Closure Method 40
2.4.3 Package-Level Deformation 42
2.4.4 Energy Release Rate for Stand-Alone Chips 42
2.5 Energy Release Rate Under Chip-Package Interactions 45
2.5.1 Effect of Low-k Dielectrics 45
2.5.2 Effect of Solder Materials and Die Attach Process 46
2.5.3 Effect of Low-k Material Properties 47
2.6 Effect of Interconnect Scaling and Ultralow-k Integration 50
2.7 Summary 54
vii
viii Contents
Acknowledgments 55
References 56
CHAPTER 3
Mechanically Compliant I/O Interconnects and Packaging 61
3.1 Introduction 61
3.2 Compliant I/O Requirements 63
3.3 Overview of Various Compliant Interconnect Technologies 63
3.3.1 FormFactor’s MOST 63
3.3.2 Tessera’sμBGA and WAVE 64
3.3.3 Floating Pad Technology 65
3.3.4 Sea of Leads 65
3.3.5 Helix Interconnects 66
3.3.6 Stress-Engineered Interconnects 67
3.3.7 Sea of Polymer Pillars 68
3.3.8 Elastic-Bump on Silicon Technology 69
3.4 Design and Analysis of Compliant Interconnects 69
3.4.1 Design Constraints 69
3.5 Case Study on Trade-Offs in Electrical/Mechanical Characteristics
3.5 of Compliant Interconnects 71
3.6 Reliability Evaluation of Compliant Interconnects 73
3.6.1 Thermomechanical Reliability Modeling 73
3.7 Compliant Interconnects and Low-k Dielectrics 76
3.8 Assembly of Compliant Interconnects 78
3.9 Case Studies: Assembly of Sea of Leads and G-Helix Interconnects 78
3.10 Integrative Solution 80
3.11 Summary 83
References 83
CHAPTER 4
Power Delivery to Silicon 87
4.1 Overview of Power Delivery 87
4.1.1 Importance of Power Delivery 87
4.2 Power Delivery Trends 88
4.3 The Off-Chip Power Delivery Network 90
4.3.1 Voltage Droops and Resonances on the Power Delivery
4.3.1 Network 91
4.3.2 Current-Carrying Capability 93
4.4 dc-dc Converter 94
4.4.1 Motivation for dc-dc Converter 94
4.4.2 Modeling 95
4.4.3 Circuits 98
4.4.4 Measurements 99
4.5 Linear Regulator 100
4.5.1 Motivation 100
4.5.2 Modeling 101
4.5.3 Circuits 102
Contents ix
4.5.4 Measurements 104
4.6 Power Delivery for 3D 106
4.6.1 Needs for 3D Stack 106
4.6.2 3D-Stacked DC-DC Converter and Passives 108
4.7 Conclusion 109
References 109
CHAPTER 5
On-Chip Power Supply Noise Modeling for Gigascale 2D and 3D Systems 111
5.1 Introduction: Overview of the Power Delivery System 111
5.2 On-Chip Power Distribution Network 113
5.3 Compact Physical Modeling of the IR-Drop 113
5.3.1 Partial Differential Equation for the IR-Drop of a
5.3.1 Power Distribution Grid 113
5.3.2 IR-Drop of Isotropic Grid Flip-Chip Interconnects 115
5.3.3 Trade-Off Between the Number of Pads and Area
5.3.1 Percentage of Top Metal Layers Used for Power Distribution 118
5.3.4 Size and Number of Pads Trade-Off 118
5.3.5 Optimum Placement of the Power and Ground Pads for an
5.3.5 Anisotropic Grid for Minimum IR-Drop 119
5.4 Blockwise Compact Physical Models for ΔI Noise 119
5.4.1 Partial Differential Equation for Power Distribution Networks 120
5.4.2 Analytical Solution for Noise Transients 122
5.4.3 Analytical Solution of Peak Noise 124
5.4.4 Technology Trends of Power-Supply Noise 127
5.5 Compact Physical Models for ΔI Noise Accounting for Hot Spots 128
5.5.1 Analytical Physical Model 128
5.5.2 Case Study 131
5.6 Analytical Physical Model Incorporating the Impact of 3D Integration 134
5.6.1 Model Description 134
5.6.2 Model Validation 136
5.6.3 Design Implication for 3D Integration 137
5.7 Conclusion 139
References 140
CHAPTER 6
Off-ChipSignaling 143
6.1 Historical Overview of Off-Chip Communication 143
6.2 Challenges in Achieving High-Bandwidth Off-Chip
6.2 Electrical Communication 147
6.2.1 System-on-a-Chip Impact of Large-Scale I/O Integration 147
6.2.2 Pad Capacitance: On-Chip Low-Pass Filters 148
6.2.3 Reflections Due to Impedance Discontinuities and Stubs 150
6.2.4 Dielectric and Skin-Effect Loss and Resulting Intersymbol
6.2.4 Interference 150
6.2.5 Interference and Noise 151
6.2.6 Timing and Jitter 152