Table Of Content

lndex IEE Proceedings Computers and Digital Techniques Vol. 146, 1999 Author Index ; Lam, K.P. p68 Lam, S.P. p107 : ‘ Lee, G. p302 Falkowski, B.J _p4l Lee, N.-Y. p259 A Fleury, M. p22 Lee, N.Y. pl19 i Fong, A.S pl07 Lin. T.-Y p264 Acan, A. p77 G ILl :ori sA, Ap. 2 [pl Almaini, A.E.A. p197 z . B M BBBByealsnlatidcrnikoi,bv, ,u rMn L,.A . pSp.21Rp2.71 139 7 p185 : HHoa,n , W.THH.H. . pp112838 MMMMMaaeaaechncsiezitirra,i,i n, no i,,EAP . .. K .M Ppp..1 1A77.3p3 ,p9, 21 1 1ppp 222282131 Huang, J.-D. p131 Mohanty, B.K. p91 . Hung, S.-L. p16 Cc Hwang, M.-S. p219 Hwang, S.H. p188 O Camarda, P. p3322 Hwang, T. p259 Chang, C.-C. p83 Orencik, B CChhaanngg,, CT..--SH.. pp34019 Ortega, J Chang, Y.-R. p253 Ozguner, Chen, J.-J. p275 ] Chen, S.-J. p275 Chen, S.-S. p j P CCCC—Clhhhhaieue¥ r,nunu ka ,gn,n S, gg a.,,TAA A ..RCeFS.F..P - .PPp.-.JY. .2pK24IB S p23 p 52 + 74 1p 13 JJJoeosnuih,, a nnCJe..-s«- Y,W., . F.pMp1.33 10 9 p21 PPPPPPP;iaaoea esronrrcre,ckiai ttilomeln,weDlaosl s,.,ik wC, i.a ,WrLM .Gab.. i n 3M,p2". 1App p.131 S721.0o30 e 7, pp39p0 222 1 D Khalil, M.A. p295 5 , oF Kia, S.M. p9 DDoeMwincthoenl,i , A.GC.. ppl2723 _ KKuiom,, JF..HH.. pp122355 SSaanltlia,y . P.B p2p1211 | Drechsler, R. p302 Scotti, M.V. p13 I Shen, V.R.L. p235 E 1% Shen, W.-Z pl31 Zhang, ( Shiu, U.-M. p241 Zhu, H.W a ‘ Lai, F. p235 Solana, J.M. p283 Zhuang. N Eisenmann, H. p21 Lam, K.-W. pl61 Stenz, G. p21 Elsaholy, M.S. p247 IEE Proc. - Comput. Digit. Tech., Vol 146, 1999 Subject Index DIGITAL TECHNIQUES Automatic selection of instruction op-codes of low-power core processors p173 Fuzzy time point compatibility reasoning for microprocessor systems p68 ARTIFICIAL INTELLIGENCE Instruction cache prefetching directed by branch prediction p241 Fuzzy time point compatibility reasoning for microprocessor systems pos ENGINEERING COMPUTING AUTOMATA THEORY Automatic router for the pin grid array package p275 Compiler/hardware co-design for instruction boosting in ILP processors p269 Application of symbolic FSM Markovian analysis to protocol verification p221 Encoding in Roth-Karp decomposition with application to two-output LUT architec- Exact AEP model in signature analysis using LCM p247 ture pl31 Graph-based detailed router for hierarchical field-programmable gate arrays p57 CIRCUIT THEORY AND DESIGN Power-driven technology mapping using pattern-oriented power modelling p83 PTM: technology mapper for pass-transistor logic p13 fest and diagnosis of faulty logic blocks in FPGAs p100 Graph-based detailed router for hierarchical field-programmable gate arrays p57 Power-driven technology mapping using pattern-oriented power modelling p83 FEEDBACK PTM: technology mapper for pass-transistor logic p13 Technology mapping for simultaneous gate and interconnect optimisation p21 Exact AEP model in signature analysis using LCM p247 CMOS INTEGRATED CIRCUITS FORMAL LOGIC Design of a fast radix-4 SRT divider and its VLSI implementation p205 Versatile architecture for block matching motion estimation p188 Efficient polarity conversion for large Boolean functions p197 Encoding in Roth-Karp decomposition with application to two-output LUT architec- CODES AND DECODING ture pl3l Fuzzy time point compatibility reasoning for microprocessor systems p68 Haar spectra-based entropy approach to quasi-minimisation of FBDDs p41 Efficient polarity conversion for large Boolean functions p197 Encoding in Roth-Karp decomposition with application to two-output LUT architec- INTEGRATED CIRCUITS ture pl31 = Integrated approach for fault tolerance and digital signature in RSA p151 Automatic router for the pin grid array package p275 COMMUNICATION SYSTEM THEORY Exact AEP model in signature analysis using LCM p247 Power-driven technology mapping using pattern-oriented power modelling p83 Wafer-scale diagnosis tolerating comparator faults p211 Analytic modelling of locking protocols in database systems p161 Application of symbolic FSM Markovian analysis to protocol verification p 221 Design of BAG3 network architecture p139 LOGIC CIRCU - Performance evaluation of TCP/IP protocol implementations in end systems p32 Design of a fast radix-4 SRT divider and its VLSI implementation p205 COMPUTATIONAL COMPLEXITY Encoding in Roth-Karp decomposition with application to two-output LUT architecture p13 ETDD-based synthesis of two-dimensional cellular arrays for multi-output incom- Efficient algorithms for binary logarithmic conversion and addition p168 pletely specified Boolean functions p302 Exact AEP model in signature analysis using LCM p247 COMPUTER COMMUNICATIONS Graph-based detailed router for hierarchical field-programmable gate arrays p57 Hardware-efficient implementations for discrete function transforms using LUT- Application of symbolic FSM Markovian analysis to protocol verification p22 PASbaEs-esdc anF PGdAessi gn:p 30a 9 new full-scan structure to reduce test application time p283 Design of BAG3 network architecture p139 PTM: technology mapper for pass-transistor logic p13 Self-checking synchronous controller design p9 DATA COMMUNICATION Technology mapping for simultaneous gate and interconnect optimisation p21 Test and diagnosis of faulty logic blocks in FPGAs p100 Analytic modelling of locking protocols in database systems p16I Application of symbolic FSM Markovian analysis to protocol verification p221 LOGIC DESIGN Design of BAG3 network architecture p139 Performance evaluation of TCP/IP protocol implementations in end systems p32 Compiler/hardware co-design for instruction boosting in ILP processors p269 Design of a fast radix-4 SRT divider and its VLSI implementation p205 DATA HANDLING Efficient conversion algorithms for long-word-length binary logarithmic numbers and logic implementation p295 Application of symbolic FSM Markovian analysis to protocol verification p221 Efficient polarity conversion for large Boolean functions p197 Encoding in Roth-Karp decomposition with application to two-output LUT architec- SItnutdeyg ratofe d ana pepfrfoicaicehn t fsori muflaualtti ont olemreatnhcoe d andp 25di3g ital signature in RSA p151 ture pl31 ETDD-based synthesis of two-dimensional cellular arrays for multi-output incom- pletely specified Boolean functions p302 DATA SECURITY Exact AEP model in signature analysis using LCM p247 Graph-based detailed router for hierarchical field-programmable gate arrays p57 (t.n) threshold verifiable multisecret sharing scheme based on factorisation intracta- PHAaaSrE -sscpeacnt rad-ebsaisgend: ae ntnreowp y fualpl-psrcoaanc h strtuo ctquurae sit-om irneidmuicsea titeosnt aopfp lFicBaDtiDosn tpim4ei p283 bility and discrete logarithm modulo a composite problems p264 Correctness of CHW cryptographic key assignment scheme in a hierarchy p217 Power-driven technology mapping using pattern-oriented power modelling p83 PTM: technology mapper for pass-transistor logic p13 CCrryyppttaannaallyyssiiss oafn da ipmubplriocv ekmeeyn tc ryopf toPseytsetresme n-pMriocphoeslesd sbiyg ncWruy ptainodn Dsacwhesmoen pp112835 Self-checking synchronous controller design p9 Cryptographic key assignment scheme for dynamic access control in a user hierarchy Technology mapping for simultaneous gate and interconnect optimisation p21 p235 Test and diagnosis of faulty logic blocks in FPGAs p100 Extension of CHW cryptographic key assignment scheme in a hierarchy p219 Wafer-scale diagnosis tolerating comparator faults p211 Integrated approach for fault tolerance and digital signature in RSA p15] Security of Shao’s signature schemes based on factoring and discrete logarithms MATHEMATICAL TECHNIQUES p119 Threshold proxy signatures p259 Graph-based detailed router for hierarchical field-programmable gate arrays p57 Hardware-efficient implementations for discrete function transforms using LUT- DATABASE MANAGEMENT SYSTEMS based FPGAs p309 Analytic modelling of locking protocols in database systems p161 MICROPROCESSORS DIGITAL ARITHMETIC Automatic selection of instruction op-codes of low-power core processors p173 Design of a fast radix-4 SRT divider and its VLSI implementation p205 MULTIPROCESSOR SYSTEMS Efficient algorithms for binary logarithmic conversion and addition pl68 Efficient conversion algorithms for long-word-length binary logarithmic numbers and logic implementation p295 Analysis of failure recovery schemes for distributed shared-memory systems p125 Design and implementation of fault-tolerant and cost effective crossbar switches for multiprocessor systems p50 DIGITAL ELECTRONICS Design of BAG3 network architecture p139 Dynamic scheme for reducing hot-spot effects in multipath networks p179 Hardware implementation of RAM-based neural networks for tomographic data Highly fault-tolerant hypercube multicomputer p77 processing pll14 NEURAL NETWORKS DIGITAL FILTERS Hardware implementation of RAM-based neural networks for tomographic data High throughput and low-latency implementation of bit-level systolic architecture for processing pll4 iD and 2D digital filters p91 Study of an efficient simulation method p253 318 IEE Proc. - Comput. Digit. Tech., Vol 146, 1999 NUMERICAL ANALYSIS Highly fault-tolerant hypercube multicomputer p77 Instruction cache prefetching directed by branch prediction p24] Cryptanalysis of a public key cryptosystem proposed by Wu and Dawson p185 Performance evaluation of TCP/IP protocol implementations in end systems p32 Study of an efficient simulation method p253 Test and diagnosis of faulty logic blocks in FPGAs p1l00 OPTICAL COMMUNICATION PRODUCTION ENGINEERING Design of BAG3 network architecture p139 Automatic router for the pin grid array package p275 OPTICAL IMAGE PROCESSING Wafer-scale diagnosis tolerating comparator faults p211 Hardware implementation of RAM-based neural networks for tomographic data SEMICONDUCTOR STORAGE processing p114 Versatile architecture for block matching motion estimation p188 Hardware implementation of RAM-based neural networks for tomograp OPTIMISATION processing pll4 SIMULATION, MODELLING AND IDENTIFICATION Automatic selection of instruction op-codes of low-power core processors p173 Enctuordei ngp l3inl Roth-Karp decomposition with application to two-output LUT architec Dynamic scheme for reducing hot-spot effects in multipath net Nondeterministic AND-EXOR minimisation by using rewrite rules and simulated Efficient algorithms for binary logarithmic conversion and 1dditi annealing pl Study of an efficient simulation method p253 Parallel implementation of simulated annealing using transaction processing p107 SOFTWARE TECHNIQUES PARALLEL PROCESSING Analysis of failure recovery schemes listributed sh CDeoesmmsipiugigl nlt eirpar/ndoh ca1e risdmswopairmlprl e em seynscttoae-tt mdiesos ni gpno 5f f0 f fofar auullitt-n-tst torluecratnito nt anbdo oansd ctoistn gt eeffifnf eeccIttLi Pv e prcroocsessbstao rr s swipt2tcc6hhe9se s ff or CFAounzmazplyyit liect ri/mmeh oadrpedolwilanitrn eg c omcopfo a-tdlieobsciiklgiinntg y foprrr oetaoisncsootlnrs i ng tiino fno rd abtmoaiobcsartsoiepn rg osc in sIsoLr P psryoscteesmsso r Design of BAG3 network architecture p139 Highly fault-tolerant hypercube multicomputer p77 STATISTICAL ANALYSIS Parallel implementation of simulated annealing using transaction processing p107 Scheduling schemes for data farming p2927 Analytic modelling of locking protocols in database systems Application of symbolic FSM Markoviar inalysis to protoc PATTERN RECOGNITION SWITCHING THEORY Hardware implementation of RAM-based neural networks for tomographic data Verpsratoiclees sianrgc hitpecltlu4r e for block matching motion estimation p188 EATpDplDi-cbataisoend of sysnytmhbeoslisi c ofF StMw o-Mdiamreknosviioanna l ancaellylsuilsa r t [ ays fool r vmeurilftiic-aotiuotnp ut m pletely specified Boolean functions p302 PERFORMANCE EVALUATION Haar spectra-based entropy approach to quasi-minimisation of FBDDs p41 Nondeterministic AND-EXOR minimisation by using rewrite rules and simul Analysis of failure recovery schemes for distributed shared-memory systems p125 annealing pl Design and implementation of fault-tolerant and cost effective crossbar switches for Self-checking synchronous controller design p9 multiprocessor systems p50 Technology mapping for simultaneous gate and interconnect optimisation Dynamic scheme for reducing hot-spot effects in multipath networks p179 IEE Proc. - Comput. Digit. Tech., Vol 146, 1999