HW support for operating systems and applications

85 Pages·2013·4.93 MB·English

ARTEMIS JU
ARTEMIS-2009-1
Reduced Certification Costs for Trusted Multi-
core Platforms (RECOMP)

Deliverable D3.4
HW support for operating systems, applications and monitoring

Nature: Report Dissemination Level: Confidential

Grant Agreement number: 100202
Project acronym: RECOMP
Project title: Reduced Certification Costs for Trusted Multi-core Platforms
Funding Scheme: ARTEMIS JU
Date of latest version of Annex I
against which the assessment will
be made:
Periodic report: Third Periodic Report
Period covered: From 1/10/2011 to 1/04/2013

Project coordinator name,
title and organization: Jarkko Makitalo, KONE
Tel: [phone]
Fax: [phone]
E-mail: [email protected]

Project website address: http://www.recomp.eu
DELIVERABLE SUMMARY

The deliverable for Task3.4- “HW support for operating systems, applications and monitoring” is summarized as
follows

Target for month 18 is:
Requirements for the OS and Application taken from WP1
Motivation for the multiple platforms to be developed
The concepts and an implementation plan for each hardware prototype platforms to support OS and
Applications

Target for month 36 is:
Detailed description of architectures and implementations of hardware prototype platforms to support OS
and Applications
Sections on evaluation of each prototype platform
Table of Contents
1. TASK INTRODUCTION ..................................................................................................................................................... 8
1.1. OBJECTIVES ACCORDING TO THE TECHNICAL ANNEXE ..................................................................................................................... 8
1.1.1. TASK Description in Technical Annexe .......................................................................................................................... 8
1.1.2. Deliverable Description in Technical Annexe ................................................................................................................ 8
1.1.3. Differences from Descriptions in Technical Annexe ..................................................................................................... 8
1.2. MILESTONES AND DELIVERABLES ................................................................................................................................................ 9
1.3. TASK 3.4 AND ITS RELATION TO OTHER WORKPACKAGES AND WP3 TASKS. ....................................................................................... 9
2. PLATFORMS INTRODUCTION ....................................................................................................................................... 10
3. IDAMC (TUBS) .............................................................................................................................................................. 11
3.1. OVERVIEW OF PLATFORM. ..................................................................................................................................................... 11
3.1.1. Tiles ............................................................................................................................................................................. 11
3.1.2. Network-On-Chip ........................................................................................................................................................ 12
3.1.3. Platform ...................................................................................................................................................................... 13
3.1.4. Overview of Mechanisms ............................................................................................................................................ 14
3.2. DETAILED DESCRIPTION OF MECHANISMS .................................................................................................................................. 14
3.2.1. Virtualization ............................................................................................................................................................... 14
3.2.2. Monitoring and Control .............................................................................................................................................. 16
3.2.3. Quality of Service ........................................................................................................................................................ 18
3.2.4. Core-to-Core Communication ..................................................................................................................................... 19
3.2.5. Fault-Tolerance ........................................................................................................................................................... 20
3.3. DEPLOYMENT AND USAGE BY PARTNERS .................................................................................................................................... 20
3.4. EVALUATION OF PLATFORM AGAINST RECOMP GOALS ............................................................................................................... 20
3.4.1. Technology Readiness Level (TRL) ............................................................................................................................... 20
3.4.2. Contribution to the state of the art ............................................................................................................................ 20
4. TRUSTED COMPUTE PLATFORM (IFX) ........................................................................................................................... 22
4.1. OVERVIEW OF PLATFORM ...................................................................................................................................................... 22
4.2. DESCRIPTION OF EXISTING RECOMP RELEVANT MECHANISMS ...................................................................................................... 24
4.2.1. Address Protection (MPU) .......................................................................................................................................... 24
4.2.2. I/O Protection Level .................................................................................................................................................... 25
4.2.3. Atomic Operations ...................................................................................................................................................... 25
4.3. DESCRIPTION OF MECHANISM ENHANCEMENTS .......................................................................................................................... 25
4.3.1. Task Isolation Enhancements ...................................................................................................................................... 25
4.3.2. Privileged Task “Virtualisation” ................................................................................................................................... 26
4.3.3. System Peripheral and Memory Protection ................................................................................................................ 26
4.3.4. New Atomic Operations .............................................................................................................................................. 28
4.3.5. Interrupt Mechanism Enhancements ......................................................................................................................... 28
4.3.6. Core 2 Core Communication Requirement Evaluation ............................................................................................... 29
4.4. DEPLOYMENT AND USAGE BY PARTNERS .................................................................................................................................... 29
4.5. EVALUATION OF PLATFORM AGAINST RECOMP GOALS ............................................................................................................... 29
4.5.1. Technology Readiness Level (TRL) ............................................................................................................................... 30
4 [Hardware support for Operating Systems, applications and monitoring]
4.5.2. Contribution to the state of the art ............................................................................................................................ 30
5. AVIONIC COMPUTING PLATFORM (7SOLUTIONS) ........................................................................................................ 31
5.1. OVERVIEW OF PLATFORM ...................................................................................................................................................... 31
5.1.1. AION board (processors board) .................................................................................................................................. 32
5.1.2. RECOMP Sensor Board (RSB) ...................................................................................................................................... 34
5.1.3. FUNCTIONAL ARCHITECTURE ACP (AION+RSB)........................................................................................................... 36
5.2. DETAILED DESCRIPTION OF MECHANISMS .................................................................................................................................. 44
5.2.1. Mechanisms for the implemented AMP and SMP architectures ................................................................................ 44
5.3. DEPLOYMENT AND USAGE BY PARTNERS .................................................................................................................................... 46
5.4. EVALUATION OF PLATFORM AGAINST RECOMP GOALS ............................................................................................................... 47
5.4.1. Technology Readiness Level (TRL) ............................................................................................................................... 48
5.4.2. Contribution to the state of the art ............................................................................................................................ 49
5.5. DISSEMINATION REPORT ........................................................................................................................................................ 49
6. CAMEA PLATFORM ...................................................................................................................................................... 51
6.1. OVERVIEW OF PLATFORM ...................................................................................................................................................... 51
6.1.1. CPU .............................................................................................................................................................................. 51
6.1.2. FPGA ............................................................................................................................................................................ 54
6.2. DETAILED DESCRIPTION OF MECHANISMS .................................................................................................................................. 55
6.2.1. Isolation ....................................................................................................................................................................... 57
6.2.2. Fault tolerance for FPGA ............................................................................................................................................. 57
6.3. DEPLOYMENT AND USAGE BY PARTNERS .................................................................................................................................... 58
6.4. EVALUATION OF PLATFORM AGAINST RECOMP GOALS ............................................................................................................... 58
6.4.1. Technology Readiness Level (TRL) ............................................................................................................................... 59
6.5. DISSEMINATION REPORT ........................................................................................................................................................ 59
7. SDU PLATFORM ........................................................................................................................................................... 60
7.1. SOC HARDWARE OVERVIEW .................................................................................................................................................. 60
7.1.1. SoC Hardware Architecture Model ............................................................................................................................. 60
7.2. DEPLOYMENT AND USAGE BY PARTNERS .................................................................................................................................... 61
7.3. EVALUATION OF PLATFORM AGAINST RECOMP GOALS ............................................................................................................... 62
8. THALES PLATFORM ...................................................................................................................................................... 63
8.1. OVERVIEW OF PLATFORM ...................................................................................................................................................... 63
8.2. DETAILED DESCRIPTION OF MECHANISMS .................................................................................................................................. 64
8.2.1. Isolation ....................................................................................................................................................................... 64
8.2.2. Fault tolerance ............................................................................................................................................................ 64
8.2.3. Core to core Communications .................................................................................................................................... 64
8.2.4. Virtualisation ............................................................................................................................................................... 64
8.3. DEPLOYMENT AND USAGE BY PARTNERS .................................................................................................................................... 65
8.4. EVALUATION OF PLATFORM AGAINST RECOMP GOALS ............................................................................................................... 65
8.4.1. Technology Readiness Level (TRL) ............................................................................................................................... 65
9. EADS (EADS IW + EADS DE) PLATFORMS ...................................................................................................................... 66
9.1. OVERVIEW OF PLATFORMS ..................................................................................................................................................... 66
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9.1.1. FPGA TUBS .................................................................................................................................................................. 66
9.1.2. Freescale P4080 .......................................................................................................................................................... 68
9.2. DETAILED DESCRIPTION OF MECHANISMS .................................................................................................................................. 69
9.2.1. FPGA TUBS .................................................................................................................................................................. 69
9.2.2. Freescale P4080 .......................................................................................................................................................... 70
9.3. DEPLOYMENT AND USAGE BY PARTNERS .................................................................................................................................... 71
9.3.1. FPGA TUBS .................................................................................................................................................................. 71
9.3.2. Freescale P4080 .......................................................................................................................................................... 71
9.4. EVALUATION OF PLATFORM AGAINST RECOMP GOALS ............................................................................................................... 71
9.4.1. FPGA TUBS .................................................................................................................................................................. 71
9.4.2. Freescale P4080 .......................................................................................................................................................... 72
10. PAJ PLATFORM. ........................................................................................................................................................... 73
10.1. UPDATE TO FINAL VERSION .................................................................................................................................................... 73
10.2. OVERVIEW OF PLATFORM ...................................................................................................................................................... 73
10.2.1. Processor Board .......................................................................................................................................................... 73
10.2.2. I/O Board ..................................................................................................................................................................... 73
10.3. DETAILED DESCRIPTION OF MECHANISMS .................................................................................................................................. 74
10.4. CORE2CORE COMMUNICATION .............................................................................................................................................. 75
10.5. DEVELOPMENT SYSTEM .................................................................................................................................................. 75
10.6. DEPLOYMENT AND USAGE BY PARTNERS .................................................................................................................................... 75
11. METSO AUTOMATION ................................................................................................................................................. 76
11.1. SHORT DEMONSTRATOR HARDWARE AND SOFTWARE DESCRIPTION ............................................................................................... 76
12. DEMONSTRATIONS AND PROTOYPES .......................................................................................................................... 77
13. CONCLUSIONS .............................................................................................................................................................. 78
14. REQUIREMENTS INDEX ................................................................................................................................................ 79
15. REFERENCES ................................................................................................................................................................. 82
6 [Hardware support for Operating Systems, applications and monitoring]
List of Figures
Figure 1: IDAMC Overview ........................................................................................................................................... 11
Figure 2: Tile Overview .................................................................................................................................................. 12
Figure 3: Architecture of the IDAMC NoC Switch ........................................................................................................ 13
Figure 4: HAPS Board Layout [4] .................................................................................................................................. 13
Figure 5: Address Translation ......................................................................................................................................... 14
Figure 6: Interrupt Translation ........................................................................................................................................ 15
Figure 7: Shared Resource Monitoring ........................................................................................................................... 16
Figure 8: Power Monitoring ............................................................................................................................................ 17
Figure 9: Interrupt Monitoring ........................................................................................................................................ 18
Figure 10: 2 NoC Switches with Back Suction ............................................................................................................... 18
Figure 11: Core to core communication ......................................................................................................................... 19
Figure 12: Trusted Compute Platform. ........................................................................................................................... 22
Figure 13: Functional Overview of the TCP ................................................................................................................... 23
Figure 14: Block diagram of the functions within the Virtual Microcontroller .............................................................. 23
Figure 15: Subset of virtual microcontroller with RECOMP enhanced IP in yellow. .................................................... 24
Figure 16: Avionic Computing Platform. ....................................................................................................................... 31
Figure 17: Physical Interface connection between boards. ............................................................................................. 32
Figure 18: AION board ................................................................................................................................................... 32
Figure 19: RECOMP Sensor Board. ............................................................................................................................... 35
Figure 20: Quad-core Leon3 architecture ....................................................................................................................... 43
Figure 21: Overall AX32 Platform architecture with interfaces between FPGA and main CPU. .................................. 51
Figure 22: Toradex Colibri PXA320 Interface Block Diagram. ..................................................................................... 52
Figure 23: Toradex Colibri PXA320 front side .............................................................................................................. 52
Figure 24: Toradex Colibri PXA320 back side. .............................................................................................................. 52
Figure 25. Toradex Colibri T20 front side. ..................................................................................................................... 53
Figure 26: Toradex Colibri T20 back side. ..................................................................................................................... 53
Figure 27: Toradex Colibri T20 Interface Block Diagram. ............................................................................................ 53
Figure 28: AX32 Platform with Toradex Colibri T20 module. ...................................................................................... 54
Figure 29: Bottom side of AX32 Platform with application expansion conector. .......................................................... 55
Figure 30: Illustration to CPU load-monitoring interface (a) and signal timings (b). ..................................................... 56
Figure 31: Slice utilization ratios for AX32/Spartan6 implementations of the hardware interrupt limiter unit. ............ 56
Figure 32: Maximum buffers (utilized to store data of all data w.r.t. stalled/deferred interrupts) realizable on-chip of
the AX32/Spartan6 along with the hardware interrupt limiter unit. ............................................................................... 57
Figure 33. AX32 Platform poster presentation at Intertraffic 2012 in Amsterdam. ....................................................... 59
Figure 34: The hardware architecture model for the HARTEX Multikernel .................................................................. 60
Figure 35: The HARTEX multikernel architecture ........................................................................................................ 61
Figure 36: C2C interconnection on a Altera Platform .................................................................................................... 62
Figure 37: Multicore Architecture on FPGA .................................................................................................................. 63
Figure 38: Xilinx VC707 development board ................................................................................................................. 64
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Figure 39: IDAMC Architecture ..................................................................................................................................... 66
Figure 40: Virtex-6 FPGA ML605 Evaluation Kit ......................................................................................................... 67
Figure 41: IDAMC Example implementation................................................................................................................. 67
Figure 42: Freescale P4080 architectural block diagram ................................................................................................ 69
Figure 43: Memory Protection in Freescale P4080......................................................................................................... 70
Figure 44: Planned architectural deployment of voting cores......................................................................................... 71
Figure 45: Outline of the two connected processor boards. ............................................................................................ 73
Figure 46: The Nios® II core from Altera Corporation. ................................................................................................. 74
Figure 47: Traditional Design ......................................................................................................................................... 75
Figure 48: Virtual MultiCore Design .............................................................................................................................. 75
Figure 49: Block diagram of Metso Automation Demonstrator. .................................................................................... 76
1. TASK INTRODUCTION
This deliverable describes Hardware Support for Operating Systems and Applications in safety critical systems
implemented using multi-core devices.
1.1. OBJECTIVES ACCORDING TO THE TECHNICAL ANNEXE
1.1.1. TASK Description in Technical Annexe
The following text is taken directly from the Technical Annexe description of Task 3.4 ‘HW support for operating
systems, applications and monitoring’ (page 51):
The HW support developed in 3.1 and 3.2 must be implemented in real HW architectures to be used by 3.3 and 3.5.
This requires availability of an executable platform. Sufficiently accurate simulators are too slow for intense work
in OS development. The large variety of target HW architectures prevents the use of a fixed HW architecture as a
basis. Therefore, emulators shall be used. IFX UK will provide an FPGA platform for high-end multi-core
architectures based on TriCore that can be used by Delphi FR, CEA and EBA. Furthermore IFX UK will provide
hardware mechanisms/components to enable runtime monitoring.
SDU will investigate its operating system implementation in hardware using a soft-processor or dedicated
hardware logic on reprogrammable logic devices. BUT, PAJ, EADS-IW, EADS-DE, Thales, ISEP and TUBS will
develop an alternative, more generic platform on FPGA-based emulators to be used for multi-core developments.
This platform will incorporate the developed concepts for virtualization and run-time power and performance
monitoring from Tasks 3.1-3.3. Appropriate library modules, such as based on a Leon core, will be provided. . In
this context ISEP will investigate the optimisation HW support for achieving greater accuracy of the proposed
power monitoring and bus contention methods and will provide corresponding solutions. Especially the bus
contention methods will have a direct impact on the models used in WP2. MA and Camea will develop suitable HW
modules for their automation applications. 7S will provide multi-core FPGA platform for avionics applications that
will be used by INT to integrate their middleware.
1.1.2. Deliverable Description in Technical Annexe
The following text is taken directly from the Technical Annexe List off Deliverables Task 3.4 ‘HW support for
operating systems and applications: Concept, Implementation, Evaluation. Draft report’ (page 22):
This deliverable contains the outcome of task 3.4. It consists of a report and a hardware prototype. A draft report
will present the concept and an implementation plan while the final report will also explain the implementation and
will contain a section on evaluation. A hardware prototype will be available at T0+18, a demonstration of the
hardware platform will be given at the end of the project (T0+36).
1.1.3. Differences from Descriptions in Technical Annexe
There are some changes from the Technical Annexe description of HW development for Task 3.4
The Technical Annexe description could be read as implying all of BUT, PAJ, EADS-IE, EADS-DE, Thales and
TUBS would develop and work on a single platform. The actual co-operations are
BUT worked with CAMEA on a platform for industrial applications.
EADS-IE/DE evaluated the TUBS IP for a platform as well as a COTS multiprocessor, described in Section 9.
Thales FR worked on an FPGA board that incorporate the NoC developed by TUBS to develop their own
platform.
Metso Automation. altered their participation in WP3.4, which is described in Section 11.
ISEP developed monitoring principles rather than a platform
PAJ will develop their own FPGA platform, and will have some cooperation with SDU. For the first report they
were behind in implementation of their platform, but stated an intention to catch up in the next period. The change
since the first report is outline in section 10.1.
For completeness, we record that
TUBS have executed on their plans for a many core architecture based around a network on chip.
Seven Solutions’ (ACP) platform has been implemented and delivered to several partners for both WP5 and
WP3.5 integration tasks of HW and SW.
[ARTEMIS JU RECOMP Deliverable3.4] 9
IFX (TCP) platform has been implemented and delivered to several partners with effective development of both
SW and Demonstrators.
SDU FPGA platform has been completed and usable for WP3.5 integration activities despite some partner
difficulties.
1.2. MILESTONES AND DELIVERABLES
All the milestones and deliverables of T3.4 are listed in Table 1.
Table 1: Milestones and deliverables
Milestone [M] / Deliverable [D] Due date
HW support for operating systems, applications and monitoring
Draft Report 1/10/2011
Final Report 1/04/2013

1.3. TASK 3.4 AND ITS RELATION TO OTHER WORKPACKAGES AND WP3
TASKS.
Task 3.4 is intended to define both hardware concepts and produced concrete implementations prototyped in FPGAs
(typically). These concepts and prototypes should support the mechanisms defined in Task 3.1 for Virtualisation
(Isolation) and Monitoring, Task 3.2 for Core-to-Core Communication and if necessary take additional functionality
required from Task 3.3 for any needs from Operating Systems for the support of RECOMP goals.
In a safety development, it is key to have a very strong focus on the requirements. However, in this task the
connection with the requirements is indirect. The requirements from Work Package 1 Research Drivers, which pulled
together the requirements (business case, technical and safety), are passed through Task 3.1, 3.2 and 3.3 into this task.
Task 3.5 involves the integration of the software (Operating Systems from Task 3.3 + Applications SW) and the
hardware developed in this task 3.4. The initial evaluation of the Task 3.4 hardware commenced in the integration
work in of Task 3.5 – and continued on into the full bring up of application systems in the Demonstrator activities of
WP5. At this stage (Final report at T0 + 36), these developments are mostly complete and many integration activities
have been successful even if i) more effort has been expended than expected (prediction of effort in a research
programme is necessarily an inexact science) and ii) the certifiability of systems has not been proven out. It is clear the
learnings for all the partners in RECOMP have been more than the development effort itself.
10 [Hardware support for Operating Systems, applications and monitoring]
2. PLATFORMS INTRODUCTION
As will become clear in the following sections, the platforms developed as prototypes by the RECOMP partners are
many and varied. There is variation both in the industrial and research areas targeted, - for example industrial markets
covering Aerospace, Automotive, and several Industrial control domains, and perhaps more importantly in the
technical approach taken.
In the Aerospace area, the ACP platform is taking the technically interesting (and unusual compared to the other
prototypes) approach that the dual cores are isolated except for a mailbox between them. In addition, there are some
interesting practical approaches – with both the development of an open source board, with a clear distinction between
the processor board (with high reuse) and an application specific board to contain the sensors and actuators which will
change with every application, (even within the same target space of aeronautical systems).
In the Automotive area, the TCP platform takes advantage of a commercial processor with an automotive focus to add
safety features in a virtual prototype of a product – using a crossbar for both shared communication, and for
supporting system configurations performance isolation as well
The AX32 adds hardware to manage interrupt overload conditions for commercially available processors, guarantees
about interrupts being of serious concern in hard realtime systems.
The SDU Hartex system investigates a more fully connected system (supporting broadcast communication in constant
time) which is not the case for other systems. The PAJ prototype takes a commercially available interconnect
RapidIO®.
The raison d’être of RECOMP was to consider the opportunity of the multi core processor to reduce development (or
redevelopment) effort and in some case enable more economic safety systems. The advent of the multicore era,
beginning with dual core processors is not a fixed point in time –PCs and computer servers have had dual core
processor for so long that modern processors targeting these markets no longer have only two cores! Yet, in some
industrial applications, dual core products are just arriving, and in yet others it will be several years before they are
commonplace. In addition, in many of these dual and multicore products there is very little focus on safety features or
on enabling the reuse goals of RECOMP.
Meanwhile, not only must we look to coming multicore products, we must look beyond multicore to the many-core
era. Whilst this is only just touched on in RECOMP, it is healthy to see that both the IDAMC platform from TUBS
and the Thales (FR) platform investigates the use of many-cores system with a NoC as the interconnect. The many-
core execution environment is one that will have both unique safety as well as exploitation and porting challenges.