High Speed and Wide Bandwidth Delta-Sigma ADCs

180 Pages·2013·5.56 MB·English

High Speed and Wide Bandwidth
Delta-Sigma ADCs
M. Bolatkale
.
High Speed and Wide Bandwidth
Delta-Sigma ADCs
Proefschrift
ter verkrijging van de graad van doctor
aan de Technische Universiteit Delft,
op gezag van de Rector Magnificus prof. ir. K.C.A.M. Luyben,
voorzitter van het College voor Promoties,
in het openbaar te verdedigen
op dinsdag 22 october 2013 om 12:30 uur
door
Muhammed BOLATKALE,
Master’s Degree in Electronic Engineering
Delft University of Technology, The Netherlands
geboren te Kahramanmaraş,Turkey.
Dit proefschrift is goedgekeurd door de promotoren:
Prof. dr. ir K.A.A. Makinwa
Prof. dr. ir. L.J. Breems
Samenstelling promotiecommissie:
Rector Magnificus voorzitter
Prof. dr. ir. K.A.A. Makinwa Technische Universiteit Delft, promotor
Prof. dr. ir. L.J. Breems Technische Universiteit Eindhoven, promotor
Prof. dr. ir. Ing. M. Ortmanns Ulm University, Germany
Prof. dr. ir. R.B. Staszewski Technische Universiteit Delft
Prof. dr. ir. B. Nauta Universiteit Twente
Dr. ir. M.A.P. Pertijs Technische Universiteit Delft
Dr. ir. M. Pelgrom Pelgrom Consulting
Prof. dr. ir. E. Charbon Technische Universiteit Delft, reservelid
The researchdescribedinthis thesiswasfundedbyNXPSemiconductorsB.V.
Published and distributed by: Ipskamp Drukkers B.V.
ISBN 978-94-6191-877-2
Copyright (cid:2)c 2013 by M. Bolatkale
All rights reserved. No part of the material protected by this copyright notice
may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying, recording or by any information storage
and retrieval system, without written permission of the author.
Printed in The Netherlands
Aileme ve bana destek olan tüm herkese
To my parents and to the people who have supported me

Contents
Contents
Glossary ix
1 Introduction 13
1.1 Trends in Wide Bandwidth and High Dynamic Range ADCs . 15
1.2 Motivation and Objectives . . . . . . . . . . . . . . . . . . . . . 16
1.3 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . 18
2 Continuous-Time Delta-Sigma Modulator 23
2.1 Ideal Delta-Sigma Modulator . . . . . . . . . . . . . . . . . . . 23
2.1.1 System Overview . . . . . . . . . . . . . . . . . . . . . . 23
2.1.2 Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.1.3 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.1.4 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2 System-Level Non-Idealities . . . . . . . . . . . . . . . . . . . . 35
2.2.1 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.2 Non-Linearity . . . . . . . . . . . . . . . . . . . . . . . . 39
2.2.3 Excess Loop Delay . . . . . . . . . . . . . . . . . . . . . 41
2.2.4 Metastability . . . . . . . . . . . . . . . . . . . . . . . . 47
2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3 Continuous-Time Delta-Sigma Modulators at High Sampling
Rates 55
3.1 System-Level Design . . . . . . . . . . . . . . . . . . . . . . . . 56
3.1.1 CTΔΣ Modulator Design at High Sampling Rates . . . 56
3.1.2 ExcessLoopDelayCompensationwithanActiveAmplifier 59
3.1.3 High-Speed Capacitive Feedforward CT ΔΣ Modulator 65
v
Contents
3.2 Block-LevelDesign Requirements . . . . . . . . . . . . . . . . . 70
3.2.1 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.2.2 Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.2.3 Feedback DAC (DAC1) . . . . . . . . . . . . . . . . . . 86
3.2.4 Quantizer DAC (DAC2) . . . . . . . . . . . . . . . . . . 90
3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4 A 4GHz Continuous-Time ΔΣ ADC 99
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2 Implementation Details . . . . . . . . . . . . . . . . . . . . . . 100
4.2.1 CTΔΣ ADC Architecture . . . . . . . . . . . . . . . . . 100
4.2.2 Quantizer Design and Timing Diagram of the Modulator 101
4.2.3 Feedback DACs . . . . . . . . . . . . . . . . . . . . . . . 104
4.2.4 Operational Transconductance Amplifier . . . . . . . . . 106
4.2.5 Decimation Filter. . . . . . . . . . . . . . . . . . . . . . 107
4.3 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . 108
4.3.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . 108
4.3.2 Measurement Results . . . . . . . . . . . . . . . . . . . 109
4.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
5 A 2GHz Continuous-Time ΔΣ ADC with Dynamic Error Cor-
rection 123
5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.2 Dynamic Error Correction Techniques in ΔΣ Modulators . . . 129
5.2.1 The Error Switching Technique . . . . . . . . . . . . . . 134
5.3 Multi-Mode High-Speed ΔΣ ADC Design . . . . . . . . . . . . 137
5.4 Implementation Details . . . . . . . . . . . . . . . . . . . . . . 139
5.4.1 Input Stage and the Loop Filter . . . . . . . . . . . . . 139
5.4.2 Pulse Generator . . . . . . . . . . . . . . . . . . . . . . 141
5.5 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . 144
5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6 Conclusions 151
6.1 Benchmarking. . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
A Comparison of ADC Architectures 157
B Non-linearity of an Ideal Quantizer 161
Summary 163
vi
Contents
Samenvatting 167
List of publications 171
About the author 173
Acknowledgments 175
vii