high speed ADC design

29 Pages·2007·3.58 MB·English

1
Trends in high speed ADC design
Akira Matsuzawa
Department of Physical Electronics
Tokyo Institute of Technology
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2007.10.27 ASICON A. Matsuzawa && OOkkaaddaa LLaabb..
Contents
2
• Introduction
• Technology scaling and performance of
pipelined ADCs
– Performance model of pipelined ADC
• Design challenge of high speed ADCs
– Pipelined ADCs
• Optimization of OpAmp
• Comparator controlled Current source
in stead of OpAmp
– Sub-ranging ADC
– Successive approximation ADCs
– Delta-sigma ADC
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2007.10.27 ASICON A. Matsuzawa && OOkkaaddaa LLaabb..
Speed and power
3
Conversion speed has saturated at 200 MHz
Smaller mW/MHz is needed for low power operation.
0.3mW/MHz for 10bit and 1mW/MHz for 12bit are the bottom lines.
High Speed ADC
[Sampling Freq. VS Power]
JSSC,ISSCC,VLSI
10000
,CICC,ESSCC
12b
10b
& Products
(≧10Bit,≧
10MSps)
1000 1995-2006
12bit :1mW /MHz
]
W
10bit :0.3mW /MHz
m
[ 100
r
e
w
o
P
12Bit(Paper)
10
200MHz 10Bit(Paper)
12Bit Products
ISSCC 2007
10Bit Products.
1
1 10 100 1000 10000
Sampling Freq.[MSps]
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2007.10.27 ASICON A. Matsuzawa && OOkkaaddaa LLaabb..
Pipelined ADC
4
Folding I/O characteristics makes higher resolution along with pipeline stages.
Hold Sample Amplify
Transfer characteristics
1st Stage 2nd Stage
Sample Sample
1st stage Amp. Amp. +V +V
ref ref
-V +V -V +V
ref ref ref ref
0 1 0 1
0 1
Amp. Amp.
2nd Stage Sample Sample
Ｘ２ -V Ｘ２ -V
ref ref
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2007.10.27 ASICON A. Matsuzawa && OOkkaaddaa LLaabb..
Technology scaling for analog
5
Technology scaling can reduce parasitic capacitances.
However signal capacitance will increase to keep the same SNR at
lower voltage operation.
(cid:1)(cid:1)(cid:1)(cid:1)
Parasitic capacitance smaller (cid:1)(cid:1)(cid:1)(cid:1)
Signal capacitance larger
(cid:1)(cid:1)(cid:1)(cid:1)
Operating voltage lower (cid:1)(cid:1)(cid:1)(cid:1)
Voltage gain lower
(cid:1)(cid:1)(cid:1)(cid:1)
Signal swing lower
V :l arge
Vdd sig Technology Vdd V : small
M5 M5 sig
scaling
Vbp1 Vbp1
Vbp1 Vbp1
Signal
Vbp2 Vbp2 Signal
Cap.
Cap.
Voutp Voutn Voutp Voutn
Vinn Vinp Vbn2 Vinn Vinp Vbn2
Parasitic
Parasitic
Cap.
Cap.
Parasitic
Parasitic
Vbn1 Vbn1 Parasitic
Cap.
Cap.
Cap.
Parasitic
Cap.
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2007.10.27 ASICON A. Matsuzawa && OOkkaaddaa LLaabb..
Performance model for pipelined ADC
6
We have developed the performance model for pipeline ADC that can treat
technology scaling.
Cf
A. Matsuzawa, “Analog IC Technologies for Future
OpAmp Wireless Systems,”IEICE, Tan on Electronics, Vol. E89-
C, No.4, pp. 446-454, April, 2006.
1
g
s GBW = m β
1+ _close 2πC
ω
Cs C C R C L
gm p2
pi po L OL
C
β= f
C +C +C
f s pi
( )
g :Transconductanceofinputstage C C +C
m
f s pi
C ,C :Signalcapacitance for feedbackloop C = C +C +
s f L po oL
C +C +C
C ,C :input& putput paraciticcapacitance f s pi
pi po
C :Loadcapacitance C +C
oL
R :Outputresistance C = s f C = C = C = C
L oL o s f oL
2
ω :Second poleof OpAmp
p2
g 1 I 1
GBW = m = ds
_close 2πC  C  C   C  πC V  α I  α I   α I 
o 2+ pi 1+ po +1+ pi  o eff 2+ pi ds 1+ po ds +1+ pi ds 
         
 C  C   C   C  C   C 
o o o o o o
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2007.10.27 ASICON A. Matsuzawa && OOkkaaddaa LLaabb..
Scaling and analog device and circuit parameters
7
D
I
ds Gate width and capacitances decrease with technology scaling.
C C
gd db
(a)W ,W [μm/mA],V , V [V]
G N P A_N A_P
B
V =0.175V
C C eff
DR
gs sb
2L
W = I 　
C μC V 2 ds
db
ox eff
S
1000
C
]
z gs
H
G W
] (b)C , C C [fF/mA],ω ,ω [GHz]
[ A 100 pi_N pi_P, po p2_N p2_P
T
f m C
A], m/ gd DR
m
μ
/
F [
f W
[
10
.
p
a f
C T
1/S2
S: Scaling factor
1
0.1 0.2 0.3 0.4 0.5
L[μm]
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2007.10.27 ASICON A. Matsuzawa && OOkkaaddaa LLaabb..
Determination of signal capacitance
8
Larger resolution requires larger signal capacitance.
Furthermore, Voltage lowering increases signal capacitance more.
2
 
2N
 
C ≥ 1.66 ×10−19
V
 
dd o V
 
sig
2V
eff
1000
Output
14bit
signal 100
v Gain v
V V out out- range
Boost
in+ in-
+ amp. Vdd-4Veff 10 12bit
]
F
p
[ 1
o 10bit
C
2V 0.1
eff
8bit
0.01
9900nnmm 00..1133μμμμμμμμmm 00..1188μμμμμμμμmm 00..2255μμμμμμμμmm 00..3355μμμμμμμμmm
0.001
VV 11..22VV 11..55VV 11..88VV 22..55VV 33..33VV 0.05 0.1 0.5
dddd
VV 11..00VV 11..66VV 22..22VV 33..66VV 55..22VV DR[μm]
ssiigg__pppp
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2007.10.27 ASICON A. Matsuzawa && OOkkaaddaa LLaabb..
Performance curve
9
Performance exhibits convex curve.
There is the peak conversion frequency and the optimum current.
Current increase results in increase of parasitic capacitances and decrease of
conversion frequency in the higher current region.
I 1
GBW = ds
_close πC V  α I  α I   α I 
o eff 2+ pi ds 1+ po ds  + 1+ pi ds 
    
 C  C   C 
o o o
10000C = 50fF
②
o ①C ≫C ,C
o po pi
③ I 1
① GBW ≈ ds ・ （ ∝ I ）
_close πC V 3 ds
o eff
1000
②C <C ＜C
] pi o po
z
H
M 1 1
[ GBW ≈ ・ 　（Constant）
fc _close πC V 3+α
o eff o
100
③C ＜C 、C ＜C
o po o pi
1 1 1
10 GBW ≈ ・ （ ∝ ）
0.01 0.1 1 10 _close πC V 3 +αα I I
o eff i o ds ds
Ids[mA]
90nm 0.13μm 0.18μm 0.25μm 0.35μm
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2007.10.27 ASICON A. Matsuzawa && OOkkaaddaa LLaabb..
Performance summary
10
Scaled CMOS is effective for just low resolution ADC.
Scaled CMOS is not effective for high resolution ADC.
10000 10000
1000 1000
] ]
z z
H H
M 100 M 100
[ [
c c
f f
10 10
８bit 10bit
1 1
0.01 0.1 1 10 0.01 0.1 1 10
Ids[mA] Ids[mA]
90nm 0.13μm 0.18μm 0.25μm 0.35μm 90nm 0.13μm 0.18μm 0.25μm 0.35μm
1000 100
100 10
z] z]
MH 10 MH 1
c[ c[
f f
1 0.1
1122bbitit 14bit
0.1 0.01
0.01 0.1 1 10 0.01 0.1 1 10
Ids[mA] Ids[mA]
90nm 0.13μm 0.18μm 0.25μm 0.35μm 90nm 0.13μm 0.18μm 0.25μm 0.35μm
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2007.10.27 ASICON A. Matsuzawa && OOkkaaddaa LLaabb..