High-Performance Digital VLSI Circuit Design

321 Pages·1996·8.762 MB·English

by  Richard X. Gu, Khaled M. Sharaf, Mohamed I. Elmasry (auth.)

HIGH-PERFORMANCE DIGITAL
VLSI CIRCUIT DESIGN
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
VLSI, COMPUTER ARCHITECTURE AND
DIGITAL SIGNAL PROCESSING
Consulting Editor
Jonathan Allen
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HIGH-PERFORMANCE DIGITAL
VLSI CIRCUIT DESIGN
by
Richard X. Gu
University of Waterloo
Khaled M. Sharaf
University of Waterloo
Mohamed 1. Elmasry
University of Waterloo
"~.
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
ISBN 978-1-4613-5970-8 ISBN 978-1-4615-2297-3 (eBook)
DOI 10.1007/978-1-4615-2297-3
Library of Congress Cataloging-in-Publication Data
A C.I.P. Catalogue record for this book is available
from the Library of Congress.
Copyright ~ 1996 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 1996
Softcover reprint of the hardcover Ist edition 1996
AII rights reserved. No part of this publication may be reproduced, stored in
a retrieval system or transmitted in any form or by any means, mechanical,
photo-copying, recording, or otherwise, without the prior written permission of
the publisher, Springer Science+Business Media, LLC
Printed on acid-free paper.
To
Steven Koo, Shu-Chuan Wang, David Koo, Eric Gu, Jiehua Yu
and Shan-Zhi Wang
Sharaf's family
Elizabeth, Carmen, Samir, Nadia and Hassan Elmasry
CONTENTS
PREFACE
~
1 INTRODUCTION 1
1.1 Comparisons Between Bipolar and MOS Transistors 2
1.2 CMOS Digital Circuits 3
1.3 Bipolar ECL Circuits 3
1.4 BiCMOS Circuits 5
1.5 Power-Delay Tradeoffs Between CMOS, Bipolar ECL and
BiCMOS Circuits 6
1.6 BOOK ORGANIZATION 7
REFERENCES 9
2 DEVICE DESIGN CONSIDERATIONS 11
2.1 Design Considerations for MOSFETs 11
2.1.1 Threshold Voltage 12
2.1.2 Body Effect 12
2.1.3 Breakdown Voltage 14
2.1.4 Short-Channel Effects 14
2.1.5 Hot Carrier Effects 17
2.1.6 Latchup in CMOS 17
2.2 Design Considerations for Bipolar Transistors 20
2.2.1 Current Gain 21
2.3 Cutoff Frequency 25
2.3.1 Breakdown Voltages 28
2.3.2 Reachthrough Voltage 29
2.3.3 Base-Emitter Punchthrough 29
viii HIGH-PERFORMANCE DIGITAL VLSI CIRCUIT DESIGN
2.3.4 Parasitic Resistances 30
2.3.5 Junction Capacitances 32
2.4 BiCMOS Device Design Considerations 32
2.5 BiCMOS Device Scaling 34
2.5.1 MOS Device Scaling 35
2.5.2 Bipolar Device Scaling 37
2.6 Chapter Summary 40
REFERENCES
~
3 DEVICE MODELING 47
3.1 Modeling of the MOS Transistor 47
3.1.1 MOSFET Structure and Operation 47
3.1.2 SPICE Models of the MOS Transistor 51
3.1.3 Analytical Model for Short-Channel MOS Devices
[13] 76
3.2 Modeling of the Bipolar Transistor 78
3.2.1 BJT Structure and Operation 78
3.2.2 Ebers-Moll Model 81
3.2.3 Bipolar Models in SPICE 90
3.3 Chapter Summary 95
REFERENCES 97
4 CMOS HIGH-PERFORMANCE CIRCUITS 99
4.1 Static Digital CMOS Circuits 99
4.1.1 Conventional CMOS Logic 100
4.1.2 Self-Bootstrapping Method 100
4.1.3 Pseudo-NMOS Logic 101
4.1.4 Adaptively-Biased Pseudo-NMOS Logic (APNL) 102
4.1.5 CMOS Nonthreshold Logic (NTL) 104
4.1.6 Pseudo Diode-Transistor Logic 104
4.1.7 Complementary Pass-Transistor Logic (CPL) 105
4.1.8 Double Pass-Transistor Logic (DPL) 106
4.2 Non-Pipelined Dynamic CMOS Circuits 106
4.2.1 Domino CMOS Logic 108
Contents ix
4.2.2 N-P Domino CMOS Logic 109
4.2.3 Multiple-Output Domino Logic (MODL) 110
4.2.4 Zipper Logic 112
4.2.5 Casco de Voltage Switch Logic (CVSL) 113
4.3 Pipelined Dynamic CMOS Circuits 113
4.3.1 Clocked CMOS C2MOS Logic (C2MOS) 114
4.3.2 Four-Phase Precharge-Discharge CMOS Logic 115
4.3.3 NO Race (NORA) Logic 115
4.3.4 True-Single-Phase-Clock Logic (TSPC) 115
4.4 An All-N-Logic Single-Phase Pipelined Dynamic CMOS Logic 119
4.4.1 Circuit Structures and Operational Principles 119
4.4.2 Circuit Optimization and Evaluation 126
4.4.3 Circuit Examples 133
4.4.4 Experimental Results 134
4.5 CHAPTER SUMMARY 139
REFERENCES 141
5 A CML PROPAGATION DELAY MODEL 143
5.1 Introduction 143
5.2 CML and ECL Previous Delay Models 143
5.3 New CML Propagation Delay Model 146
5.3.1 Model Derivation 146
5.4 Transient Analysis 149
5.4.1 Preliminary 149
5.4.2 Superposition of Delay Times 150
5.4.3 Delay Analysis 152
5.4.4 Total Propagation Delay 161
5.5 High-Current Effects 163
5.6 Model Verification and Its Application in Circuit Optimiza-
tion 166
5.7 Model Limitations 174
5.8 Chapter Summary 175
REFERENCES 177
x HIGH-PERFORMANCE DIGITAL VLSI CIRCUIT DESIGN
6 SERIES-GATED CML AND ECL BIPOLAR
CIRCUITS 179
6.1 Introduction 179
6.2 Two-level Series-gating CML and ECL Circuit Design 179
6.3 Analysis and Optimization of Two-level Circuits 181
6.3.1 Preliminary 181
6.3.2 Formulation of the Propagation Delay Model 182
6.3.3 Optimization on Device and Circuit Levels 182
6.4 Series-Gated CML and ECL Circuits 182
6.4.1 Basic 2-Level XOR Circuit 184
6.4.2 High-Current Effects 188
6.4.3 Emitter-Follower Stage 189
6.4.4 Circuit Configuration, Loading and Fanout 191
6.5 Results and Model Verification 192
6.6 Model Applications in Optimizing CML and ECL Series-
Gated High-Speed Circuits 195
6.6.1 Optimizing the XOR Circuit 195
6.6.2 Optimizing Static Frequency Dividers 198
6.6.3 Optimizing Dynamic Frequency Dividers 201
6.7 Chapter Summary 203
REFERENCES 205
7 HIGH-PERFORMANCE BICMOS CIRCUIT
STRUCTURES 207
7.1 Introduction 207
7.2 ECL/CMOS Interface Circuits 208
7.2.1 Simulation Results 210
7.3 Dynamic ECL Reference Voltage (DRV) CMOS/ECL In-
terface Circuits 214
7.3.1 A Conventional CMOS/ECL Interface Circuit 214
7.3.2 The Operation Principle of the DRV-CMOS/ECL In-
terface Circuit 216
7.3.3 DC Characteristics and Noise Margins 219
7.3.4 Transient Analysis 221
7.3.5 Results and Design Considerations 228
Contents xi
7.4 BiCMOS Sense Amplifiers for SRAM 231
7.4.1 Sense Amplifier Examples 232
7.4.2 A BiCMOS Sense Amplifier 234
7.5 CHAPTER SUMMARY 239
REFERENCES 241
8 HIGH-PERFORMANCE CML, ECL AND NTL
BICMOS CIRCUITS 245
8.1 Introduction 245
8.2 Low-Power Circuits and Systems 246
8.3 BJT and MOS Series-Gated CML Circuit Techniques 247
8.4 Performance of XOR, D-Iatch BJT and MOS Series-Gated
Circuits 249
8.5 Performance of CML D-Latch Comparator Circuits 253
8.6 High-Performance ECL Circuit Techniques 259
8.7 Active Load (Series Diode and Resistor) 259
8.8 Active-Pull-Down Techniques 260
8.8.1 AC-Coupled Active-Pull-Down Emitter-Follower Stage 260
8.8.2 Charge-Buffered Active-Pull-Down ECL Circuit 261
8.8.3 AC-Coupled Complementary Push-Pull ECL Circuit 261
8.8.4 Capacitor-Coupled Complementary Emitter-Follower
ECL Circuit 261
8.8.5 Self-Adjusting Active-Pull-Down ECL Circuit 264
8.8.6 Cross-Coupled Active-Pull-Down ECL Circuit 264
8.8.7 Feedback-Controlled Active-Pull-Down ECL Circuit 264
8.8.8 NMOS Active-Pull-Down ECL Circuit 264
8.8.9 NMOS/Bipolar Active-Pull-Down ECL Circuit 265
8.9 Discussion and Assessment of Active-Pull-Down ECL Cir-
cuit Techniques 266
8.10 BiCMOS Active-Pull-Down ECL Circuit Technique 266
8.11 Non-Threshold-Logic Circuits 274
8.12 Conventional NTL Circuits 274
8.12.1 Front-End Stage 274
8.12.2 Emitter-Follower Stage 276
8.13 APD-NTL Circuit Techniques 276