High-Performance D/A-Converters: Application to Digital Transceivers

296 Pages·2013·6.411 MB·English

by  Martin Clara (auth.)

High-Performance D/A-Converters
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Martin Clara
High-Performance
D/A-Converters
Application to Digital Transceivers
123
MartinClara
LANTIQ-AGmbH
Villach
Austria
ISSN1437-0387
ISBN978-3-642-31228-1 ISBN978-3-642-31229-8(eBook)
DOI10.1007/978-3-642-31229-8
SpringerHeidelbergNewYorkDordrechtLondon
LibraryofCongressControlNumber:2012954677
(cid:2)c Springer-VerlagBerlinHeidelberg2013
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Preface
D/A-converterssynthesize analog signals at the very heart of digital transceivers,
thuslinkingtheworldofdigitalsignalprocessingtotheanalogsignaldomain.The
integrationofthe digitalsignalprocessor(DSP) togetherwith data convertersand
analogsignalprocessingfunctionsinadvancedCMOStechnologiesfinallyenables
the realization of complete transceivers on a single silicon chip. This so-called
system-on-chip(SoC)integrationdrasticallyreducesthecostandtheformfactorof
theoverallsystem,ahighlydesirablesituationincost-drivenhardwaredevelopment.
The topic of this work is the modeling and the implementation of high-
performancecurrent-steeringD/A-convertersfor digital transceiversin nanometer
CMOS technology. To comply with the target of SoC integration, the designed
convertermodules are fully embeddablein a mixed-signalsystem. They use only
core devices, operate from a single supply voltage, and are optimized for small
siliconareaandlow-powerdissipation.
In the first part of this book the fundamental performance limitations of
current-steering DACs are investigated. Based on simplified models, closed-form
expressionsforanumberofbasicnonidealeffectsarederivedandtested.Aspecial
focusisputonthesignal-dependentnoiseperformanceinmultitonesystems,show-
ingthatthetraditionalfull-scalesingle-tonecriteriaarenotadequateandmaylead
tosubstantialoverdesignofbiasingand/orclockingcircuits.Theknowledgeofthe
basic performancelimits allows to optimize the converterand system architecture
alreadyin an early designphase, essentially tradingoffcircuitcomplexity,silicon
area,andpowerdissipationforstaticanddynamicperformance.
Thesecondpartofthisbookdescribesthedesignandexperimentalverification
of four differentcurrent-steeringDAC testchips, implementedin standard 130nm
CMOS.Theconvertersuseasingle1.5Vsupplyandhavearesolutionintherange
of 12–14bits for an analog bandwidth between 2.2MHz and 50MHz. Sampling
ratesbetween100MHzand350MHzareused.Dynamicelementmatching(DEM)
and advanced dynamic current calibration techniques are employed to minimize
therequiredsiliconarea.High-resolutionconverterswithanactiveoutputstageto
maximizetheanalogoutputsignalswing,traditionallyonlyusedforlow-frequency
v
vi Preface
applications, are demonstrated to reach signal bandwidths of 30–50MHz, while
maintainingadynamiclinearitylargerthan70dBoverthewholebandwidth.
Thisbookisorganizedintosevenchapters:
• Chapter 1 provides an overview of D/A-converter fundamentals, especially
focusingonthecurrent-steeringarchitectureandsegmentationstrategies.
• In Chap.2 the generally accepted performance figures used to characterize
D/A-convertersarereviewed.Theimpactofcorrelatedbiasnoiseandsampling
jitteronthenoiseperformanceofacurrent-steeringDACisanalyzed,and,based
onsimplifiedmodels,exactdescriptionsofthenoisespectraforsingle-toneand
multitonesignalsarederived.Thejitternoiseexpressionsobtainedformultitone
signalsinanNRZ-DACarealsoverifiedexperimentally.
• In Chap.3 the static linearity limited by random mismatch of the current
sources is explored. Based on a statistical description of the fabrication yield,
expressionsfortherequiredminimumcurrent-sourceareafulfillingagivenyield
specification are derived. The code-dependentoutput resistance of the current-
source array is identified as a further limiting factor for the static linearity.
Expressionsforthe INL ofthe single-endedandthe fullydifferentialconverter
as a function of the finite output resistance of the unit current cell are given.
The second partof Chap.3 givesa generaloverviewof two knownmethodsto
improvethestaticlinearity:DEMandcurrentcalibration.
• Chapter 4 analyzes the three basic effects that limit the dynamic linearity of
a current-steering D/A-converter. Under the idealizing assumption of perfectly
matched current cells, which are also not influenced by any other large-scale
imperfections,itispossibleto deriveclosed-formexpressionsforthenonlinear
distortion of a synthesized sine wave. The first effect is given by switching
asymmetries that result in unsymmetrical current pulses. These are shown to
generate even-order harmonic distortion in fully differential converters. The
second effect is caused by the finite feed-through of the output voltage to
the parasitic capacitance connected at the common tail node of the current
switchpair.Theresultingcode-dependenterrorchargepacketsinjectedintothe
output generate odd-order harmonic distortion. The third effect that limits the
dynamiclinearityofacurrent-steeringD/A-converteristhefrequency-dependent
distortion due to the code-dependent output impedance of the current-source
array.Itisshownthatinafullydifferentialconverterwithstandardcurrent-cell
architecture this effect is at least within the boundaries of practical sampling
frequencies, not likely to become dominant compared to the switching errors.
Nevertheless,it isafundamentallimitationto theachievabledynamiclinearity,
since it cannot be compensated straightforwardly, e.g., by applying a special
switchingalgorithm.ThesecondpartofChap.4describesvariousknowncircuit
techniquestoimprovethedynamiclinearityofcurrent-steeringD/A-converters.
• Chapter 5 describes the implementation of two †(cid:2) D/A-converter testchips
targeted at wireline communication applications. The first design is a 14-bit
DAC targeted at the ADSL2C downstream bandwidth of 2.2MHz. It uses a
second-ordernoiseshapertogetherwithaverysimplebarrel-shiftalgorithmand
Preface vii
is optimized for low-power dissipation. The second design is a multi-mode
†(cid:2)-converter for ADSL and VDSL. An interleaved current-cell architecture
implementsan effectivereturn-to-zero(RZ) for the single currentcell and also
allows to use a modified data weighted averaging (DWA) algorithm. With a
sampling rate of 350MHz and an oversampling ratio of only 6, a dynamic
range of 12 bits in a bandwidth very close to 30MHz is demonstrated.Due to
the effective RZ, the dynamic linearity around 30MHz remains above 75dB.
The converter module is readily scalable—by register programming—tolower
signalbandwidths,withnotonlydrasticallyreducedpowerconsumptionbutalso
increasedresolution.
• InChap.6twoNyquist-rateD/A-convertertestchipsusingdynamiccurrentcali-
bration in the backgroundare described. Both designs implement a segmented
13-bit converter core. The first module is a classical, resistively terminated
single-polarityDAC, while the second converteruses a dual-polaritycore with
activetransimpedanceoutputstagetomaximizethe availablevoltageswing.In
conjunction with an interleaved current-cell architecture this DAC achieves a
signalbandwidthof50MHzwithadynamiclinearityexceeding70dBoverthe
fullsignalbandwidth.Theperiodicityofthebackgroundcalibration,normallya
source of low-frequencytonaldisturbances,is destroyedby the introductionof
a randomized calibration slot length. Thereby the calibration refresh tones are
spectrallyshapedandmergedwiththenoisefloor.Thisrandomizationalsohelps
to suppressthe image tone due to dynamiccalibration effectsin an interleaved
architecture. Two novel strategies to trim the elements in converter segments
withdifferentweightsareemployed.Thefirstdesigntriestomatchthesegment
boundaries by appropriately summing together uncalibrated and previously
calibrated DACelementsfor comparisonwith a uniquereferenceelement.The
seconddesignperformsdirectcalibrationofsingleDACelementsindifferently
weighted segments. In order to generate the required scaled reference currents
with an accurate ratio, a referencecell array is introduced,which calibrates its
constituting elements in a separate calibration loop, also running fully in the
background.
• Finally,Chap.7summarizesthemainresultsofthiswork,whiletryingtodraw
general conclusions. Also, it provides an outlook on future developments that
are expected to happen in the area of CMOS current-steering D/A-converters
targetedatdigitalcommunicationsystems.
Villach,Austria MartinClara
(cid:127)
Contents
1 Introduction .................................................................. 1
1.1 IntegratedD/A-Converters............................................. 1
1.2 DACsforHighlyIntegratedTransceivers............................. 7
1.3 TheIdealD/A-Converter............................................... 11
1.3.1 TheNonReturn-to-ZeroDAC................................ 12
1.3.2 TheReturn-to-ZeroDAC ..................................... 14
1.4 TheCurrent-SteeringDAC............................................. 16
1.4.1 GeneralDescription........................................... 16
1.4.2 Single-PolarityandDual-PolarityCurrentCells............. 18
1.4.3 PassiveandActiveOutputStage.............................. 18
1.5 ArrayCoding........................................................... 20
1.5.1 UnaryArray.................................................... 20
1.5.2 BinaryArray................................................... 21
1.5.3 SegmentedArray.............................................. 22
2 PerformanceFiguresofD/A-Converters.................................. 25
2.1 StaticAccuracy......................................................... 25
2.1.1 GainandOffsetError ......................................... 25
2.1.2 DifferentialNonlinearity...................................... 26
2.1.3 IntegralNonlinearity .......................................... 27
2.2 DynamicPerformance.................................................. 28
2.2.1 HarmonicDistortion........................................... 28
2.2.2 IntermodulationDistortion.................................... 29
2.2.3 SpuriousFreeDynamicRange................................ 30
2.2.4 DynamicRange................................................ 31
2.2.5 MultitoneLinearity............................................ 32
2.3 NoisePerformance..................................................... 35
2.3.1 Quantization“Noise”.......................................... 35
2.3.2 CircuitNoise................................................... 38
2.3.3 JitterNoise..................................................... 46
ix
x Contents
3 StaticLinearity............................................................... 63
3.1 LimitationsfortheStaticLinearity.................................... 63
3.1.1 MatchingofCurrentSources ................................. 64
3.1.2 StatisticalDescriptionoftheINL............................. 65
3.1.3 StatisticalDescriptionoftheDNL............................ 66
3.1.4 MinimumAreaRequirements ................................ 68
3.1.5 Code-DependentOutputImpedance.......................... 74
3.2 DynamicElementMatchingTechniques.............................. 78
3.2.1 ClockedLevelAveraging ..................................... 80
3.2.2 Data-WeightedAveraging..................................... 81
3.2.3 OtherDEMTechniques....................................... 82
3.3 CurrentSourceCalibration............................................. 84
3.3.1 FactoryTrimming ............................................. 85
3.3.2 Self-calibration ................................................ 86
3.3.3 LocalCalibrationDAC........................................ 88
3.3.4 GlobalCalibrationDAC....................................... 89
3.3.5 TrimmableFloatingCurrentSource.......................... 90
3.3.6 DynamicCurrentCalibration................................. 91
4 DynamicLinearity........................................................... 97
4.1 LimitationsfortheDynamicLinearity................................ 97
4.1.1 Frequency-DependentOutputImpedance.................... 97
4.1.2 AGeneralizedSwitchingErrorModel....................... 102
4.1.3 SwitchingTransitionMismatch............................... 107
4.1.4 ChargeSharingattheSwitchingNode....................... 111
4.1.5 ASPICE-SimulationExample................................ 116
4.1.6 OtherNonlinearEffects....................................... 118
4.2 MethodstoImprovetheDynamicPerformance...................... 118
4.2.1 CurrentSwitchwithReducedGateVoltageSwing.......... 119
4.2.2 SourceNodeBootstrapping................................... 122
4.2.3 SourceNodeIsolation......................................... 123
4.2.4 DifferentialQuadSwitching.................................. 124
4.2.5 ConstantDigitalActivity...................................... 125
4.2.6 Return-to-ZeroandTrack/Attenuate.......................... 126
4.2.7 DoubleReturn-to-Zero........................................ 128
4.2.8 Full-ClockInterleavedCurrentCells......................... 129
5 NoiseshapedD/A-Converters............................................... 133
5.1 A14-bitLow-PowerD/A-Converter .................................. 133
5.1.1 ConverterArchitecture........................................ 134
5.1.2 DEMSelection ................................................ 135
5.1.3 UnitCurrentCell .............................................. 136
5.1.4 Low-NoiseBiasing............................................ 138
5.1.5 OutputStage................................................... 138
5.1.6 Layout.......................................................... 139
5.1.7 ExperimentalResults.......................................... 141