High Data Rate Transmitter Circuits: RF CMOS Design and Techniques for Design Automation

237 Pages·2004·14.09 MB·English

by  Carl De Ranter, Michiel Steyaert (auth.)

HIGH DATA RATE TRANSMITTER CIRCUITS
THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND
COMPUTER SCIENCE
ANALOG CIRCUITS AND SIGNAL PROCESSING
Consulting Editor: Mohammed Ismail. Ohio State University
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HIGH DATA RATE
TRANSMITTER CIRCUITS
RF CMOS Design and Techniques
for Design Automation
by
Carl De Ranter
RF MAGIC‚ U.S.A.
and
Michiel Steyaert
KU Leuven‚ Belgium
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON, DORDRECHT, LONDON, MOSCOW
eBookISBN: 0-306-48713-6
Print ISBN: 1-4020-7545-6
©2004 Springer Science + Business Media, Inc.
Print ©2003 Kluwer Academic Publishers
Dordrecht
All rights reserved
No part of this eBook maybe reproducedor transmitted inanyform or byanymeans,electronic,
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
Visit Springer's eBookstore at: http://www.ebooks.kluweronline.com
and the Springer Global Website Online at: http://www.springeronline.com
to Ans‚
in remembrance of
Erik Grobben
Contents
List of Figures xiii
List of Tables xvii
1. INTRODUCTION 1
1.1 Some Observations 2
1.2 To CMOS or not to CMOS 4
1.3 Covered Topics 6
2. RF MODELING‚ QUADRATURE GENERATION AND FLIP-
CHIP BONDING 9
2.1 Introduction 9
2.2 Influence of Substrate Resistivity on RF-designs 10
2.2.1 A statement to start with... 10
2.2.2 A High Substrate Resistivity for Digital?! 11
2.2.3 VCO’s and Substrate Resistivity 12
2.2.4 Conclusion 13
2.3 RF-Modeling 14
2.3.1 Introduction 14
2.3.2 MOS Transistors 15
2.3.2.1 Introduction 15
2.3.2.2 Model Construction 16
2.3.2.3 ModelValidation 21
2.3.2.4 The Non-Quasi-Static Effect 25
2.3.2.5 Frequency-Performance Indicators 28
2.3.2.6 Summary 29
2.3.3 On-chip Inductors 30
2.3.3.1 Introduction 30
2.3.3.2 High-Frequency Effects 31
viii HIGH DATA RATE TRANSMITTER CIRCUITS
2.3.3.3 Inductor Parameter Prediction 33
2.3.3.4 The Use of FastHenry 39
2.3.3.5 Inductor Subcircuit for Circuit Simulation 43
2.3.4 Conclusion 46
2.4 Quadrature LO Generation 47
2.4.1 Quadrature Upconversion 47
2.4.2 Polyphase Network 51
2.4.2.1 Harmonic Polyphase Signals 51
2.4.2.2 Passive Sequence-Asymmetric Polyphase Network 54
2.4.2.3 Analytical Calculations on a Polyphase Network 55
2.4.2.4 Image Ratio 59
2.4.2.5 Loading Effects & Input Impedance 60
2.4.2.6 Simulation of a Polyphase Network used as Quadrature
Generator 62
2.4.2.7 Mismatch Effects 62
2.4.2.8 Quadrature Unbalance for Higher Harmonics 65
2.4.2.9 DesignConsiderations 66
2.4.2.l0Final Design Flow 69
2.4.3 Frequency Dividers 70
2.4.4 Conclusion 73
2.5 Manufacturing 74
2.5.1 The Bonding Process 74
2.5.2 Flip-Chip Bonding 76
2.5.2.1 Alignment Problems 77
2.5.2.2 Effect of X-ray Irradiation 78
2.6 Conclusions & Use of Presented Topics 81
3. AUTOMATED VCO SYNTHESIS 83
3.1 Introduction 83
3.2 Structured Analog Design Methodology 84
3.2.1 Definition of Functional Blocks 84
3.2.2 Structured Analog Design 86
3.2.3 Design-Level Entry Methodology 89
3.3 Automation in Functional-Block Design 92
3.3.1 Introduction 92
3.3.2 OptimizationProcess and Algorithms 92
3.3.2.1 Optimization Process 93
3.3.2.2 Cost Function Construction 94
3.3.3 Optimization Algorithms 95
Contents ix
3.3.3.1 SimulatedAnnealing 95
3.3.3.2 Evolutionary Algorithms 96
3.3.3.3 The ASA Algorithm 97
3.3.4 Template-Based Design of Functional Blocks 98
3.4 The CYCLONE Tool 105
3.4.1 Introduction 105
3.4.2 Inductor Parameter Prediction 106
3.4.3 Systematic VCO Design Methodology 106
3.4.4 Optimal Sizing of the complete VCO circuit 109
3.4.4.1 Overview of the Circuit Optimization Loop 109
3.4.4.2 Conversion of Coil Topological to Electrical Parameters
111
3.4.4.3 Cost Function 113
3.4.4.4 Evaluation Time 115
3.4.5 Layout Generation of the Complete VCO Circuit 116
3.4.5.1 Module Generator Technology 117
3.4.5.2 Template-Based Block-Repetitive Module Generator 117
3.4.5.3 Procedural VCO Placement & Route 119
3.4.5.4 Total VCO-Design Time 119
3.4.6 Design Examples - Experimental Results 120
3.4.7 Conclusions 126
3.5 Final Conclusion 127
4. VOLTAGE-CONTROLLED OSCILLATORS FOR HIGH DATA
RATE APPLICATIONS 129
4.1 Oscillators for Broadband Systems 130
4.1.1 Broadband Systems 130
4.1.1.1 In-Band LO Harmonics 130
4.1.1.2 Multi-Channel Transmission 131
4.1.2 Signal Linearization using a Polyphase Network 132
4.1.2.1 Real and Complex Signals and Filters 133
4.1.2.2 Complex Representation of a Quadrature Square Wave 134
4.1.2.3 A Polyphase Network as a Complex filter 135
4.1.2.4 Complex Filtering in Reality 145
4.1.3 Method of Waveform Construction 147
4.1.4 Chip Implementations of LO Linearization 150
4.1.4.1 LO Linearization using a Complex Filter 150
4.1.4.2 A Two ChannelTransmitter 158
4.2 Oscillators for RF Frequencies 160
x HIGH DATA RATE TRANSMITTER CIRCUITS
4.2.1 Oscillator Design Issues 161
4.2.2 Building Blocks 162
4.2.3 Power Phase Noise ? 168
4.2.4 A 17 GHz VCO in CMOS 169
4.2.5 Comparison with other Published Work 172
4.2.5.1 Table of Comparison 172
4.2.5.2 Figure-of-Merit 174
4.2.5.3 Discussion 174
4.3 Conclusions 177
5. DESIGN OF AN UPCONVERTOR FOR HIGH-SPEED DATA
TRANSMISSION 179
5.1 Introduction: Market Perspective 180
5.2 High-speed Data Link Systems 182
5.2.1 Some “Technical” Words and Concepts ... 182
5.2.2 Some “Real” Numbers for System Demands 183
5.3 High-level Design Considerations 184
5.3.1 Topology Components 185
5.3.2 Frequency Synthesizer 186
5.3.3 Quadrature Generation 187
5.3.4 Linear Mixer block 187
5.3.5 Low LO-Harmonics to avoid Spectral Regrowth 188
5.3.6 Output buffer 192
5.3.6.1 Quantification of Output Linearity 192
5.3.6.2 Buffer Requirements 193
5.4 CMOS Implementation of a High-Bandwidth Upconvertor 194
5.4.1 Introduction 194
5.4.2 Design Overview 194
5.4.2.1 Global Topology 194
5.4.2.2 Design Methodology 195
5.4.2.3 RF-MOST Model 195
5.4.3 LC-type VCO 196
5.4.3.1 Topology and Design 196
5.4.3.2 Optimization 198
5.4.4 Polyphase Network 199
5.4.5 Linear Mixer Block 200
5.4.6 Two Stage Current Buffer 202
5.4.6.1 Topology 202
5.4.6.2 Inductor Optimization 202
Contents xi
5.4.7 Chip Photo & Measurement Results 203
5.4.8 Conclusion 209
5.5 Final Conclusion 209
6. CONCLUSIONS 211
6.1 Realized Work 215
6.2 Possibilities for Future Research 216
References 217