Fundamentals of Computer Architecture and Design

541 Pages·2017·34.69 MB·English

by  Bindal

Ahmet Bindal
Fundamentals
of Computer
Architecture
and Design
Fundamentals of Computer Architecture
and Design
Ahmet Bindal
Fundamentals
of Computer
Architecture and Design
123
Dr. AhmetBindal
Computer Engineering Department
SanJose State University
SanJose, CA,USA
TheSolutions Manual for instructors canbefoundat
http://www.springer.com/us/book/9783319258096
ISBN978-3-319-25809-6 ISBN978-3-319-25811-9 (eBook)
DOI 10.1007/978-3-319-25811-9
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For my mother who always showed me the right path…
Preface
This book is written for young professionals and graduate students
whohaveprior logicdesignbackgroundandwantto learn howto use
logic blocks to build complete systems from design specifications.
Mytwo-decade-longindustryexperiencehastaughtmethatengineers
are“shape-oriented”peopleandthattheytendtolearnfromchartsand
diagrams. Therefore, the teaching method I followed in this textbook
catersthismindset:alotofcircuitschematics,blockdiagrams,timing
diagrams, and examples supported by minimal text.
Thebookhaseightchapters.Thefirstthreechaptersgiveacomplete
review of the logic design principles since rest of the chapters signifi-
cantly depend on this review. Chapter 1 concentrates on the combina-
tionallogicdesign.Itdescribesbasiclogicgates,DeMorgan’stheorem,
truth tables, and logic minimization. This chapter uses these key con-
ceptsinordertodesignmegacells,namelyvarioustypesofaddersand
multipliers.Chapter2introducessequentiallogiccomponents,namely
latches, flip-flops, registers, and counters. It introduces the concept of
timing diagrams to explain the functionality of each logic block. The
Moore and Mealy-type state machines, counter–decoder-type con-
trollers,andtheconstructionofsimplememoriesarealsoexplainedin
thischapter.Chapter2alsoillustratesthedesignprocess:howtodevelop
architectural logic blocks using timing diagrams, and how to build a
controllerfromatimingdiagramtoguidedataflow.Chapter3focuses
onthereviewofasynchronouslogicdesign,whichincludesstatedefi-
nitions,primitiveflowtables,andstateminimization.Racingconditions
in asynchronous designs, how to detect and correct them are also
explainedinthischapter.Thechapterendswithdesigninganimportant
asynchronoustimingblock:theCelement(ortheMuellerelement),and
it describes anasynchronous timing methodologythat leads to a com-
pletedesignusingtimingdiagrams.
vii
viii Preface
From Chapter 4 to Chapter 8, computer architecture-related topics
are covered. Chapter 4 examines a very essential system element:
system bus and communication protocols between system modules.
This chapter defines the bus master and the bus slave concepts and
examinestheirbusinterfaces.Readandwritebuscyclesandprotocols,
bushandoverandarbitrationarealsoexaminedinthischapter.System
memories, namely Static Random Access Memory (SRAM),
Synchronous Dynamic Random Access Memory (SDRAM),
Electrically-Erasable-Programmable-Read-Only-Memory (E2PROM)
andFlashmemoryareexaminedinChapter5.Thischapteralsoshows
how to design bus interface for each memory type using timing dia-
gramsandstatemachines.Chapter6isallaboutthedesignofasimple
Reduced Instruction Set Computer (RISC) for central processing. The
chapter starts with introducing a simple assembly instruction set and
buildingindividualhardwareforeachinstruction.Asotherinstructions
are introduced to the design, techniques are shown how to integrate
additionalhardwaretotheexistingCPUdata-pathtobeabletoexecute
multiple instructions. Fixed-point and floating-point Arithmetic Logic
Units (ALU) are also studied in this chapter. Structural, data and pro-
gram control hazards, and the required hardware to avoid them are
shown. This chapter ends with the operation of various cache archi-
tectures, cache read and write protocols, and the functionality of
write-throughandwrite-backcaches.Thedesignofsystemperipherals,
namely Direct Memory Access (DMA), interrupt controller, system
timers,serialinterface,displayadapteranddatacontrollersarecovered
in Chapter 7. The design methodology to construct data-paths with
timingdiagramsinChapter2iscloselyfollowedinthischapterinorder
todesignthebusinterfaceforeachperipheral.Chapter8describesthe
Field-ProgrammableGatearray(FPGA),andthefundamentalsofdata
driven processors as special topics.
Attheendofthebook,thereisasmallappendixthatintroducesthe
Verilog language. Verilog is a widely used Hardware Design
Language (HDL) to build and verify logic blocks, mega cells and
systems. Interested readers are encouraged to go one step beyond and
learn system Verilog to be able to verify large logic blocks.
Dr. Ahmet Bindal
Computer Engineering Department
San Jose State University
San Jose, CA, USA
Contents
1 Review of Combinational Circuits . . . . . . . . . . . . . . . . 1
1.1 Logic Gates. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Boolean Algebra. . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Designing Combinational Logic Circuits
Using Truth Tables. . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Combinational Logic Minimization—Karnaugh
Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5 Basic Logic Blocks. . . . . . . . . . . . . . . . . . . . . . . 20
1.6 Combinational Mega Cells. . . . . . . . . . . . . . . . . . 29
2 Review of Sequential Logic Circuits. . . . . . . . . . . . . . . 67
2.1 D Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.2 Timing Methodology Using D Latches . . . . . . . . . 69
2.3 D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.4 Timing Methodology Using D Flip-Flops . . . . . . . 72
2.5 Timing Violations. . . . . . . . . . . . . . . . . . . . . . . . 73
2.6 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.7 Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.8 Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.9 Moore Machine . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.10 Mealy Machine . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.11 Controller Design: Moore Machine
Versus Counter-Decoder Scheme . . . . . . . . . . . . . 90
2.12 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.13 A Design Example Using Sequential Logic
and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3 Review of Asynchronous Logic Circuits. . . . . . . . . . . . 113
3.1 S-R Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.2 Fundamental-Mode Circuit Topology . . . . . . . . . . 114
ix
x Contents
3.3 Fundamental-Mode Asynchronous
Logic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 115
3.4 Asynchronous Timing Methodology . . . . . . . . . . . 123
Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4 System Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.1 Parallel Bus Architectures . . . . . . . . . . . . . . . . . . 133
4.2 Basic Write Transfer. . . . . . . . . . . . . . . . . . . . . . 138
4.3 Basic Read Transfer . . . . . . . . . . . . . . . . . . . . . . 140
4.4 Bus Master Status Change. . . . . . . . . . . . . . . . . . 142
4.5 Bus Master Handshake . . . . . . . . . . . . . . . . . . . . 145
4.6 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.7 Bus Master Handover . . . . . . . . . . . . . . . . . . . . . 148
4.8 Serial Buses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5 Memory Circuits and Systems. . . . . . . . . . . . . . . . . . . 169
5.1 Static Random Access Memory . . . . . . . . . . . . . . 170
5.2 Synchronous Dynamic Random
Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . 179
5.3 Electrically-Erasable-Programmable-
Read-Only-Memory . . . . . . . . . . . . . . . . . . . . . . 201
5.4 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 209
5.5 Serial Flash Memory. . . . . . . . . . . . . . . . . . . . . . 253
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
6 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . 275
6.1 RISC Instruction Formats. . . . . . . . . . . . . . . . . . . 275
6.2 CPU Data-Path. . . . . . . . . . . . . . . . . . . . . . . . . . 277
6.3 Fixed-Point Register-to-Register
Type ALU Instructions . . . . . . . . . . . . . . . . . . . . 280
6.4 Fixed-Point Immediate Type ALU Instructions. . . . 292
6.5 Data Movement Instructions. . . . . . . . . . . . . . . . . 298
6.6 Program Control Instructions . . . . . . . . . . . . . . . . 302
6.7 Design Example I: A Fixed-Point CPU
with Four Instructions. . . . . . . . . . . . . . . . . . . . . 308
6.8 Design Example II: A Fixed-Point CPU
with Eight Instructions . . . . . . . . . . . . . . . . . . . . 313
6.9 Floating-Point Instructions. . . . . . . . . . . . . . . . . . 316
6.10 Floating-Point. . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Contents xi
6.11 Floating-Point Adder. . . . . . . . . . . . . . . . . . . . . . 322
6.12 Floating-Point Multiplier . . . . . . . . . . . . . . . . . . . 324
6.13 A RISC CPU with Fixed
and Floating-Point Units . . . . . . . . . . . . . . . . . . . 325
6.14 Structural Hazards. . . . . . . . . . . . . . . . . . . . . . . . 327
6.15 Data Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
6.16 Program Control Hazards. . . . . . . . . . . . . . . . . . . 333
6.17 Handling Hazards in a Five-Stage RISC CPU:
An Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
6.18 Handling Hazards in a Four-Stage RISC CPU . . . . 339
6.19 Handling Hazards in a Three-Stage RISC CPU. . . . 340
6.20 Multi-cycle ALU and Related Data Hazards. . . . . . 342
6.21 Cache Topologies. . . . . . . . . . . . . . . . . . . . . . . . 346
6.22 Cache Write and Read Structures . . . . . . . . . . . . . 349
6.23 A Direct-Mapped Cache Example. . . . . . . . . . . . . 351
6.24 Write-Through and Write-Back Cache Structures
in Set-Associative Caches . . . . . . . . . . . . . . . . . . 354
6.25 A Two-Way Set-Associative Write-Through
Cache Example . . . . . . . . . . . . . . . . . . . . . . . . . 355
6.26 A Two-Way Set-Associative Write-Back
Cache Example . . . . . . . . . . . . . . . . . . . . . . . . . 358
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
7 System Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . 377
7.1 Overall System Arcitecture. . . . . . . . . . . . . . . . . . 377
7.2 Direct Memory Access Controller. . . . . . . . . . . . . 378
7.3 Interrupt Controller. . . . . . . . . . . . . . . . . . . . . . . 387
7.4 Serial Transmitter and Receiver Interface. . . . . . . . 399
7.5 Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
7.6 Display Adaptor. . . . . . . . . . . . . . . . . . . . . . . . . 414
7.7 Data Converters . . . . . . . . . . . . . . . . . . . . . . . . . 425
7.8 Digital-to-Analog Converter (DAC). . . . . . . . . . . . 437
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
8 Special Topics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
8.1 Field-Programmable-Gate Array . . . . . . . . . . . . . . 455
8.2 Data-Driven Processors . . . . . . . . . . . . . . . . . . . . 473
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489