Fundamentals of Computer Architecture and Design

603 Pages·2019·26.96 MB·English

by  Ahmet Bindal

Ahmet Bindal
Fundamentals of
Computer Architecture
and Design
Second Edition
Fundamentals of Computer Architecture
and Design
Ahmet Bindal
Fundamentals
of Computer
Architecture and Design
Second Edition
123
AhmetBindal
Computer Engineering Department
SanJose State University
SanJose, CA,USA
ISBN978-3-030-00222-0 ISBN978-3-030-00223-7 (eBook)
https://doi.org/10.1007/978-3-030-00223-7
LibraryofCongressControlNumber:2018953318
1stedition:©SpringerInternationalPublishingSwitzerland2017
2ndedition:©SpringerNatureSwitzerlandAG2019
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For my mother who always showed me the right path.
Preface
Thisbookiswrittenforyoungprofessionalsandgraduatestudentswhohave
prior logic design background and want to learn how to use logic blocks to
build a complete system from design specifications. My two-decade-long
industry experience has taught me that engineers are “shape-oriented” peo-
ple, and that they tend to learn from charts and diagrams. Therefore, the
teaching method you will see in this textbook caters this mid-set: a lot of
circuitschematics,blockdiagrams,timingdiagrams,andexamplessupported
by minimal text.
The book has eight chapters. The first three chapters give a complete
review of the logic design principles since rest of the chapters significantly
depend on this review. Chapter 1 concentrates on the combinational logic
design.Itdescribesbasiclogicgates,DeMorgan’stheorem,truthtables,and
logic minimization. The chapter uses these key concepts in order to design
megacells, namely various types of adders and multipliers. Chapter 2 intro-
duces sequential logic components, namely latches, flip-flops, registers and
counters. It introduces the concept of timing diagrams to explain the func-
tionalityofeachlogicblock.MooreandMealy-typestatemachines,counter–
decoder-type controllers, and the construction of simple memories are also
explained in this chapter. Chapter 2 is the first chapter that illustrates the
design process: how to develop architectural logic blocks using timing dia-
grams and how to build a controller from a timing diagram to govern data
flow. Chapter 3 focuses on the review of asynchronous logic design, which
includes state definitions, primitive flow tables, and state minimization.
Racing conditions in asynchronous designs, how to detect and correct them
are also explained in this chapter. The chapter ends with designing an
important asynchronous timing block: the C (or the Mueller) element and
describes an asynchronous timing methodology that leads to a complete
design using timing diagrams.
From Chaps. 4 to 8, computer architecture-related topics are covered.
Chapter 4 examines a very essential system element: system bus and com-
munication protocols between system modules. This chapter studies parallel
and serial bus architectures, defines bus master and bus slave concepts, and
examines their bus interfaces. Read and write bus protocols, bus handover,
and bus arbitration are also examined in this chapter. System memories,
vii
viii Preface
namely static random-access memory (SRAM), synchronous dynamic-
random access memory (SDRAM), electrically erasable programmable
read-only memory (E2PROM), and flash memory are examined in Chap. 5.
This chapter also shows how to design bus interface for each memory type
using timing diagrams and state machines.
Chapter6isaboutthedesignofasimplereducedinstructionsetcomputer
(RISC)centralprocessingunit(CPU).Thischapterhasbeenexpandedinthe
second edition to cover a variety of subjects in the floating-point unit and
cache memory. In the first part of this chapter, fixed-point instructions are
introduced. This section first develops a dedicated hardware (data-path) to
execute each RISC instruction and then groups several instructions together
in a set and designs a common data-path to execute user programs that use
this instruction set. In this section, fixed-point-related structural, data and
program control hazards are described, and the methods of how to prevent
each type are explained. The second part of this chapter is dedicated to the
IEEE single and double-precision floating-point formats, leading to the
simplified designs of floating-point adder and multiplier. These designs are
thenintegratedwiththefixed-pointhardwaretoobtainaRISCCPUcapable
ofexecutingbothfixed-pointandfloating-pointarithmeticinstructions.Inthe
same section, floating-point-related data hazards are described. A new
floating-point architecture is proposed based on a simplified version of the
Tomasulo algorithm in order to reduce and eliminate these hazards. In the
thirdpart,varioustechniquestoincreasetheprogramexecutionefficiencyare
discussed. The trade-offs between static and dynamic pipelines, single-issue
versus dual-issue and triple-issue pipelines are explained with examples.
Compiler enhancement techniques, such as loop unrolling and dynamic
branch prediction methods, are illustrated to reduce overall CPU execution
time. The last section of this chapter explains different types of cache
memory architectures, including direct-mapped, set-associative and fully
associative caches, their operation and the trade-off between each cache
structure. The write-through and write-back mechanisms are discussed and
compared with each other, using design examples.
Furthermore, Chap. 6 now contains static and dynamic, single and mul-
tiple issue CPUs, the advantages of out-of-order execution and register
renaming. The final phase of this chapter is dedicated to multi-core CPUs
with a central memory and distributed memories. The data update and
replacementpolicyaredescribedforeachCPUarchitecturetomaintaincache
coherency.
The design of system peripherals, namely direct memory access (DMA),
interrupt controller, system timers, serial interface, display adapter, and data
controllers are covered in Chap. 7. The interrupt controller has been
expanded in this new edition to cover context switching. The design
methodologyforconstructingthedata-pathsusingtimingdiagramsshownin
Chap.2iscloselyfollowedtodesignthebusinterfaceforeachperipheralin
thischapter.Chapter8describesthefield-programmablegatearray(FPGA),
and the fundamentals of data-driven processors as special topics.
Preface ix
At the end of the book, there is a small appendix that introduces the
Verilog language. Verilog is a widely used Hardware Design Language
(HDL) to build and verify logic blocks, mega cells and systems. Interested
readersareencouragedtogoonestepbeyondandlearnsystemVerilogtobe
able to verify large logic blocks.
San Jose, USA Prof. Ahmet Bindal
Contents
1 Review of Combinational Logic Circuits. .... .... ..... .... 1
1.1 Logic Gates .. ..... .... .... .... .... .... ..... .... 1
1.2 Boolean Algebra.... .... .... .... .... .... ..... .... 7
1.3 Designing Combinational Logic Circuits Using
Truth Tables.. ..... .... .... .... .... .... ..... .... 9
1.4 Combinational Logic Minimization—Karnaugh Maps .... 12
1.5 Basic Logic Blocks.. .... .... .... .... .... ..... .... 18
1.6 Combinational Mega Cells .... .... .... .... ..... .... 27
2 Review of Sequential Logic Circuits. .... .... .... ..... .... 61
2.1 D Latch.. .... ..... .... .... .... .... .... ..... .... 61
2.2 Timing Methodology Using D Latches... .... ..... .... 63
2.3 D Flip-Flop... ..... .... .... .... .... .... ..... .... 64
2.4 Timing Methodology Using D Flip-Flops. .... ..... .... 65
2.5 Timing Violations... .... .... .... .... .... ..... .... 66
2.6 Register.. .... ..... .... .... .... .... .... ..... .... 71
2.7 Shift Register . ..... .... .... .... .... .... ..... .... 73
2.8 Counter.. .... ..... .... .... .... .... .... ..... .... 74
2.9 Moore Machine..... .... .... .... .... .... ..... .... 75
2.10 Mealy Machine..... .... .... .... .... .... ..... .... 79
2.11 Controller Design: Moore Versus Counter-Decoder
Scheme.. .... ..... .... .... .... .... .... ..... .... 82
2.12 Memory . .... ..... .... .... .... .... .... ..... .... 86
2.13 A Design Example Using Sequential Logic
and Memory.. ..... .... .... .... .... .... ..... .... 89
3 Review of Asynchronous Logic Circuits . .... .... ..... .... 101
3.1 S-R Latch.... ..... .... .... .... .... .... ..... .... 101
3.2 Fundamental-Mode Circuit Topology.... .... ..... .... 102
3.3 Fundamental-Mode Asynchronous Logic Circuits.... .... 102
3.4 Asynchronous Timing Methodology. .... .... ..... .... 110
4 System Bus.... .... ..... .... .... .... .... .... ..... .... 119
4.1 Parallel Bus Architectures. .... .... .... .... ..... .... 119
4.2 Basic Write Transfer. .... .... .... .... .... ..... .... 124
4.3 Basic Read Transfer . .... .... .... .... .... ..... .... 126
4.4 Bus Master Status Change .... .... .... .... ..... .... 127
4.5 Bus Master Handshake... .... .... .... .... ..... .... 129
4.6 Arbiter .. .... ..... .... .... .... .... .... ..... .... 130
xi
xii Contents
4.7 Bus Master Handover.... .... .... .... .... ..... .... 133
4.8 Serial Buses .. ..... .... .... .... .... .... ..... .... 134
5 Memory Circuits and Systems . .... .... .... .... ..... .... 151
5.1 Static Random Access Memory .... .... .... ..... .... 152
5.2 Synchronous Dynamic Random Access Memory .... .... 160
5.3 Electrically-Erasable-Programmable-Read-Only-
Memory . .... ..... .... .... .... .... .... ..... .... 181
5.4 Flash Memory. ..... .... .... .... .... .... ..... .... 189
5.5 Serial Flash Memory. .... .... .... .... .... ..... .... 229
References. .... .... ..... .... .... .... .... .... ..... .... 250
6 Central Processing Unit .. .... .... .... .... .... ..... .... 251
6.1 Fixed-Point Unit.... .... .... .... .... .... ..... .... 251
6.2 Stack Pointer and Subroutines . .... .... .... ..... .... 284
6.3 Fixed-Point Design Examples.. .... .... .... ..... .... 294
6.4 Fixed-Point Hazards . .... .... .... .... .... ..... .... 303
6.5 Floating-Point Unit.. .... .... .... .... .... ..... .... 317
6.6 Increasing Program Execution Efficiency . .... ..... .... 350
6.7 Multi-core Architectures and Parallelism . .... ..... .... 369
6.8 Caches .. .... ..... .... .... .... .... .... ..... .... 397
7 System Peripherals . ..... .... .... .... .... .... ..... .... 439
7.1 Overall System Architecture... .... .... .... ..... .... 439
7.2 Direct Memory Access Controller... .... .... ..... .... 440
7.3 Interrupt Controller.. .... .... .... .... .... ..... .... 448
7.4 Serial Transmitter Receiver Interface .... .... ..... .... 465
7.5 Timers... .... ..... .... .... .... .... .... ..... .... 472
7.6 Display Adaptor .... .... .... .... .... .... ..... .... 480
7.7 Data Converters .... .... .... .... .... .... ..... .... 489
7.8 Digital-to-Analog Converter (DAC) . .... .... ..... .... 500
8 Special Topics . .... ..... .... .... .... .... .... ..... .... 517
8.1 Field-Programmable-Gate Array.... .... .... ..... .... 517
8.2 Data-Driven Processors... .... .... .... .... ..... .... 535
Appendix: An Introduction to Verilog Hardware Design
Language... ..... .... .... .... .... .... ..... .... 551
Index ... .... .... .... ..... .... .... .... .... .... ..... .... 587