FPGA Design: Best Practices for Team-based Reuse

260 Pages·2015·8.734 MB·English

by  Philip Andrew Simpson (auth.)

Philip Andrew Simpson
FPGA
Design
Best Practices for Team-based Reuse
Second Edition
FPGA Design

Philip Andrew Simpson
FPGA Design
Best Practices for Team-based Reuse
Second Edition
Philip Andrew Simpson
San Jose , CA , USA
ISBN 978-3-319-17923-0 ISBN 978-3-319-17924-7 (eBook)
DOI 10.1007/978-3-319-17924-7
Library of Congress Control Number: 2014952901
Springer Cham Heidelberg New York Dordrecht London
© Springer International Publishing Switzerland 2010, 2015
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Contents
1 Introduction ............................................................................................. 1
2 Project Management ............................................................................... 5
2.1 The Role of Project Management .................................................... 5
2.1.1 Project Management Phases ................................................ 5
2.1.2 Estimating a Project Duration .............................................. 6
2.1.3 Schedule ............................................................................... 6
3 Design Specification ................................................................................ 9
3.1 Design Specifi cation: Communication Is Key to Success ............... 9
3.1.1 High Level Functional Specifi cation .................................... 10
3.1.2 Functional Design Specifi cation .......................................... 10
4 System Modeling ..................................................................................... 15
4.1 Defi nition of System Modeling ........................................................ 16
4.2 What is SystemC? ............................................................................ 16
4.3 Classes of SystemC Models ............................................................. 17
4.3.1 Untimed (UT)....................................................................... 17
4.3.2 Loosely-Timed (LT) ............................................................. 17
4.3.3 Approximately Timed (AT) ................................................. 18
4.3.4 Cycle Accurate ..................................................................... 18
4.4 Software Development Using Virtual Targets ................................. 18
4.5 SystemC Basics ................................................................................ 19
4.5.1 SC_Module .......................................................................... 21
4.5.2 Ports ..................................................................................... 21
4.5.3 Process ................................................................................. 21
4.5.4 SC_CTOR ............................................................................ 21
4.5.5 SC_METHOD...................................................................... 21
4.5.6 SystemC Tesbenches ............................................................ 23
5 Resource Scoping .................................................................................... 29
5.1 Introduction ...................................................................................... 29
5.2 Engineering Resources ..................................................................... 29
v
vi Contents
5.3 Third Party IP ................................................................................... 30
5.4 Device Selection .............................................................................. 30
5.4.1 Silicon Specialty Features .................................................... 31
5.4.2 Density ................................................................................. 32
5.4.3 Speed Requirements............................................................. 33
5.4.4 Pin-Out ................................................................................. 34
5.4.5 Power ................................................................................... 37
5.4.6 Availability of IP .................................................................. 37
5.4.7 Availability of Silicon .......................................................... 37
5.4.8 Summary .............................................................................. 38
6 Design Environment ............................................................................... 39
6.1 Introduction ...................................................................................... 39
6.2 Scripting Environment ..................................................................... 39
6.2.1 Make Files ............................................................................ 41
6.2.2 Tcl Scripts ............................................................................ 44
6.2.3 Automation .......................................................................... 46
6.2.4 Easier Project Maintenance and Documentation ................. 47
6.3 Interaction with Version Control Software ...................................... 48
6.4 Use of a Problem Tracking System .................................................. 48
6.5 A Regression Test System ................................................................ 49
6.6 When to Upgrade the Versions of the FPGA Design Tools ............. 49
6.7 Common Tools in the FPGA Design Environment .......................... 50
6.7.1 High-Level Synthesis ........................................................... 51
6.7.2 Load Sharing Software ........................................................ 51
7 Board Design ........................................................................................... 53
7.1 Challenges That FPGAs Create for Board Design .......................... 53
7.2 Engineering Roles and Responsibilities ........................................... 54
7.2.1 FPGA Engineers .................................................................. 55
7.2.2 PCB Design Engineer .......................................................... 55
7.2.3 Signal Integrity Engineer ..................................................... 56
7.3 Power and Thermal Considerations ................................................. 57
7.3.1 Filtering Power Supply Noise .............................................. 58
7.3.2 Power Distribution ............................................................... 58
7.4 Signal Integrity ................................................................................. 58
7.4.1 Types of Signal Integrity Problems ...................................... 59
7.4.2 Electromagnetic Interference (EMI) .................................... 60
7.5 Design Flows for Creating the FPGA Pinout................................... 60
7.5.1 User Flow 1: FPGA Designer Driven .................................. 61
7.5.2 User Flow 2 .......................................................................... 63
7.5.3 How Do FPGA and Board Engineers Communicate
Pin Changes? ....................................................................... 64
7.6 Board Design Check List for a Successful FPGA Pin-out .............. 64
Contents vii
8 Power and Thermal Analysis ................................................................. 67
8.1 Introduction .................................................................................... 67
8.2 Power Basics .................................................................................. 68
8.2.1 Static Power..................................................................... 68
8.2.2 Dynamic Power ............................................................... 68
8.2.3 I/O Power ........................................................................ 68
8.2.4 Inrush Current ................................................................. 69
8.2.5 Confi guration Power ....................................................... 69
8.3 Key Factors in Accurate Power Estimation ................................... 69
8.3.1 Accurate Power Models of the FPGA Circuitry ............. 70
8.3.2 Accurate Toggle Rate Data on Each Signal .................... 70
8.3.3 Accurate Operating Conditions ....................................... 71
8.3.4 Resource Utilization ........................................................ 72
8.4 Power Estimation Early in the Design Cycle
(Power Supply Planning) ............................................................... 72
8.5 Simulation Based Power Estimation
(Design Power Verifi cation) ........................................................... 73
8.5.1 Partial Simulations .......................................................... 75
8.6 Best Practices for Power Estimation .............................................. 76
9 Team Based Design Flow ........................................................................ 79
9.1 Introduction .................................................................................... 79
9.2 Recommended Team Based Design Flow ..................................... 80
9.2.1 Overview ......................................................................... 80
9.3 Design Set-up ................................................................................. 81
9.3.1 Creation of Top-Level Project ......................................... 82
9.3.2 Partitioning of the Design ............................................... 82
9.3.3 Timing Budgets ............................................................... 82
9.3.4 Physical Partitioning/Floorplan Design .......................... 84
9.3.5 Place and Route Design .................................................. 85
9.3.6 Create Project for Partitions/Other Team Members ........ 85
9.4 Team Member Development Flow ................................................. 85
9.5 Team Leader Design Integration .................................................... 86
9.6 Working with Version Control Software ........................................ 88
9.7 Team Based Design Checklist ....................................................... 89
10 RTL Design .............................................................................................. 91
10.1 Introduction .................................................................................... 91
10.2 Common Terms and Terminology ................................................. 92
10.3 Recommendations for Engineers with an ASIC
Design Background ........................................................................ 93
10.4 Recommended FPGA Design Guidelines ...................................... 94
10.4.1 Synchronous vs. Asynchronous ...................................... 94
10.4.2 Global Signals ................................................................. 94
10.4.3 Dedicated Hardware Blocks ............................................ 95
10.4.4 Managing Metastability .................................................. 98
viii Contents
10.5 Writing Effective HDL .................................................................. 99
10.5.1 What’s the Best Language ............................................. 100
10.5.2 Documented Code ......................................................... 101
10.5.3 Recommended Signal Naming Convention .................. 102
10.5.4 Hierarchy and Design Partitioning ................................ 103
10.5.5 Design Reuse ................................................................. 105
10.5.6 Techniques for Reducing Design Cycle Time ............... 106
10.5.7 Design for Debug .......................................................... 106
10.6 RTL Coding Styles for Synthesis ................................................... 107
10.6.1 General Verilog Guidelines ........................................... 108
10.6.2 General VHDL Guidelines ............................................ 108
10.6.3 RTL Coding for Performance ........................................ 109
10.6.4 RTL Coding for Area .................................................... 117
10.6.5 Synthesis Tool Settings ................................................. 117
10.6.6 Inference of RAM ......................................................... 118
10.6.7 Inference of ROMs ........................................................ 122
10.6.8 Inference of DSP Blocks ............................................... 128
10.6.9 Inference of Registers .................................................... 130
10.6.10 Avoiding Latches ........................................................... 134
10.7 Analyzing the RTL Design ............................................................ 136
10.7.1 Synthesis Reports .......................................................... 136
10.7.2 Messages ....................................................................... 137
10.7.3 Block Diagram View ..................................................... 137
10.8 Recommended Best Practices for RTL Design .............................. 139
11 IP and Design Reuse................................................................................ 141
11.1 Introduction .................................................................................... 141
11.2 The Need for IP Reuse ................................................................... 141
11.2.1 Benefi ts of IP Reuse ...................................................... 142
11.2.2 Challenges in Developing a Design
Reuse Methodology ....................................................... 143
11.3 Make Versus Buy ........................................................................... 144
11.4 Architecting Reusable IP ............................................................... 145
11.4.1 Specifi cation .................................................................. 145
11.4.2 Implementation Methods ............................................... 146
11.4.3 Use of Standard Interfaces ............................................ 147
11.5 Packaging of IP .............................................................................. 149
11.5.1 Documentation .............................................................. 149
11.5.2 User Interface ................................................................ 150
11.5.3 Compatibility with System Integration Tools................ 151
11.5.4 Constraint Files ............................................................. 152
11.5.5 IP Integration File Formats ............................................ 153
11.5.6 IP Security ..................................................................... 154
11.6 IP Reuse Checklist ......................................................................... 155
Contents ix
12 Embedded Design.................................................................................... 157
12.1 Defi nition of an Embedded Design ................................................ 157
12.1.1 Advantages That FPGA Devices Provide
for Embedded Design ...................................................... 159
12.2 Challenges in a FPGA Based Embedded Design .......................... 159
12.3 Embedded Hardware Design ......................................................... 160
12.3.1 Endianness....................................................................... 160
12.3.2 Busses .............................................................................. 161
12.3.3 Bus Arbitration Schemes................................................. 163
12.3.4 Hardware Verifi cation Using Simulation ........................ 165
12.4 Hardware to Software Interface ..................................................... 167
12.4.1 Defi nition of Register Address Map ............................... 167
12.4.2 Software Interface ........................................................... 167
12.4.3 Use of the Register Address Map .................................... 167
12.4.4 Summary ......................................................................... 170
12.5 Embedded SW Design ................................................................... 170
12.5.1 Firmware Development ................................................... 170
12.5.2 Application Software Development ................................ 172
12.5.3 Use of Operating Systems ............................................... 173
12.5.4 SW Tools ......................................................................... 174
12.6 Use of FPGA System Integration Tools
for Embedded Design .................................................................... 175
13 Functional Verification ........................................................................... 179
13.1 Introduction .................................................................................... 179
13.2 Challenges of Functional Verifi cation ............................................ 180
13.3 Glossary of Verifi cation Concepts ................................................. 180
13.4 RTL Versus Gate Level Simulation................................................ 181
13.5 Verifi cation Methodology .............................................................. 181
13.6 Attack Complexity ......................................................................... 182
13.7 Functional Coverage ...................................................................... 183
13.7.1 Directed Testing .............................................................. 184
13.7.2 Random Dynamic Simulation ......................................... 184
13.7.3 Constrained Random Tests .............................................. 184
13.7.4 Use of SystemVerilog for Design and Verifi cation ......... 185
13.7.5 General Testbench Methods ............................................ 186
13.7.6 Self Verifying Testbenches .............................................. 186
13.7.7 Formal Equivalency Checking ........................................ 188
13.8 Code Coverage ............................................................................... 188
13.9 QA Testing ..................................................................................... 189
13.9.1 Functional Regression Testing ........................................ 189
13.9.2 GUI Testing for Reusable IP ........................................... 189