FPGA-BASED IMPLEMENTATION OF ELECTRONIC ABACUS USING ALTERA DE2 BOARD AZMI ...

42 Pages·2017·1.49 MB·English

FPGA-BASED IMPLEMENTATION OF ELECTRONIC ABACUS USING
ALTERA DE2 BOARD

AZMI BIN SIDEK

A project report submitted in partial
fulfilment of the requirement for the award of the
Degree of Master of Electrical Engineering

Faculty of Electrical and Electronic Engineering
Universiti Tun Hussein Onn Malaysia

JULY 2017
iii

For my beloved mother, my dearest wife and children.
iv

ACKNOWLEDGEMENT

Praise to Allah upon His blessing that granted me the guidance, strength and
knowledge to complete this project.
Special appreciation to my supervisor, Assoc. Prof. Dr. Abd. Kadir bin
Mahamad for the support and guidance throughout the duration of my study. Not
forgetting my fellow colleagues who gave me the friendly environment to work
within.
A very warm gratitude to my wife, children and family that gives me their
fullest support and understanding throughout the years upon completion of my study.
Last but not least, to everyone involved directly or indirectlytowards the compilation
of this thesis.
v

ABSTRACT

The development of electronic abacus is to integrate the use of abacus along with
electronic devices which offers better visualisation of the abacus operations. The
main focus of this application is to assist the primary school students‟ in validating a
fundamental arithmetic operation by using an abacus. The electronic abacus is
developed by integrating an abacus, abacus decoder module and FPGA-based
processor. DE2 115 is chosen as the development module and VHDL as main
programming language. The arithmetic algorithm developed for the electronic abacus
is limited to the computational of whole numbers only. The electronic abacus is
operational in two modes, display mode and arithmetic mode. In the display mode,
the abacus beads position at column 1 until column 7is displayed as numerical
representation on the LCD screen. A computation of arithmetic operations with less
than three operatorsare available in the arithmetic modewith the capability
ofdisplaying the negative numerical and infinite value. The implementation of
integrating an abacus with electronic devices will hopefullycontribute in the
development of more lively and interesting teaching approach by using this ancient
apparatus.
vi

ABSTRAK

Penghasilan abakus elektronik yang menggabungkan abakus bersama peranti
elektronikdapatmenggambarkan operasi aritmetik abakus yang lebih jelas kepada
penggunanya. Digunakan sebagai alat bantuan bagi pelajar sekolah di peringkat
sekolah rendah dan sebagai pengesah operasi aritmetik bagi abakus. Abakus
elektronik dihasilkan dengan menggabungkan abakus, modul pengekodan serta
pemproses berasaskan FPGA. DE2 115 dipilih sebagai modul pembangunan dan
VHDL sebagai bahasa pengaturcaraan utama. Algoritma aritmetik yang dibangunkan
bagi abakus elektronik ini, bagaimanapun terhad kepada pengiraan untuk
nomborbulat sahaja. Abakus elektronik beroperasi dalam dua mod, iaitu mod
paparan dan mod aritmetik. Pada mod paparan, pengguna dapat melihat perwakilan
nombor pada paparan LCD yang mewakili kedudukan manik abakus pada lajur
pertama hingga lajur ke 7. Selain itu, pengiraan operasi aritmetik bagi kurang dari
tiga pengoperasi boleh dilaksanakan dalam mod aritmetik dengan keupayaan paparan
nilai negatif dan infiniti. Integrasi di antara peranti elektronik dengan abakus
diharapkan dapat membangunkanpenghasilan kaedah pembelajaran menggunakan
abakus yang lebih menarik dan bertenaga.
vii

TABLE OF CONTENTS

ACKNOWLEDGEMENT iv
ABSTRACT v
ABSTRAK vi
LIST OF TABLES x
LIST OF FIGURES xi
LIST OF SYMBOLS AND ABBREVIATIONS xiv
LIST OF APPENDICES xv
CHAPTER 1 1
INTRODUCTION 1
1.1 Introduction 1
1.2 Problem Statement 2
1.3 Objectives 2
1.4 Project Scope 3
1.5 The Organisation of Thesis 3
CHAPTER 2 5
LITERATURE REVIEW 5
2.1 Introduction 5
2.2 Abacus Historical Review 5
2.3 Abacus Architecture 8
2.4 Abacus Arithmetic Operation 9
2.4.1 Addition 10
viii

2.4.2 Subtraction 12
2.4.3 Multiplication 12
2.4.4 Division 14
2.5 Previous Related Works 16
2.6 Summary of Previous Related Works 18
CHAPTER 3 20
METHODOLOGY 20
3.1 Introduction 20
3.2 Project Activities 20
3.3 Hardware Design 21
3.4 Abacus Numerical Display and Arithmetic Algorithm 27
3.5 Experimental Configuration 30
CHAPTER 4 33
DATA ANALYSIS AND RESULTS 33
4.1 Introduction 33
4.2 Bead Sensor Circuitry and DE2 Interface Board Evaluation 33
4.3 Bead Sensor Decoder 37
4.4 Binary to ASCII Conversion 38
4.5 LCD Controller 39
4.6 Arithmetic Algorithm 40
4.6.1 Two Variables Arithmetic Operation 41
4.6.2 Three Variables Arithmetic Operation 42
4.6.2.1 Combinations of Additional Operators 43
4.6.2.2 Combinations of Subtraction Operators 46
4.6.2.3 Combinations of Multiplication Operators 47
4.6.2.4 Combinations of Division Operators 47
4.7 VHDL Evaluations 49
ix

4.8 Complete System Evaluations 51
4.8.1 Display Mode 53
4.8.2 Arithmetic Mode 53
4.8.2.1 Two Variables Mode 54
4.8.2.2 Three Variables Mode 57
CHAPTER 5 67
DISCUSSION AND CONCLUSIONS 67
5.1 Introduction 67
5.2 Discussion 67
5.3 Conclusions 70
5.4 Future Works 71
REFERENCES Error! Bookmark not defined.
APPENDIX A 76
APPENDIX B 78
APPENDIX C 80
APPENDIX D 81
APPENDIX E 82
APPENDIX F 106
x

LIST OF TABLES

2.1 Summary of previous related works 17
4.1 Binary logical levels 32
4.2 Bead position binary representation with respect 33

to numeral value
4.3 Experimental result for abacus column 7 33
4.4 Experimental result for abacus column 6 34
4.5 Experimental result for abacus column 5 34
4.6 Experimental result for abacus column 4 34
4.7 Experimental result for abacus column 3 34
4.8 Experimental result for abacus column 2 35
4.9 Experimental result for abacus column 1 35
4.10 Combinational of addition operators 42
4.11 Combinational of subtraction operators 44
4.12 Combinational of multiplication operators 45
4.13 Combinational of division operators 46
4.14 DE2 hardware and pin allocations 49
xi

LIST OF FIGURES

2.1 Salamis Tablet 6
2.2 Replica of Roman Abacus 6
2.3 Chinese abacus (2/5 suan pan) 7
2.4 Japanese abacus (soroban) 8
2.5 The evolution of counting devices 8
2.6 Japanese abacus construction and notations 9
2.7 Japanese abacus beads position and numerical 9

value
2.8 Additional Operation 10
2.9 Subtraction Operation 12
2.10 Multiplication Operation 14
2.11 Division Operation 15
3.1 Project flowchart 20
3.2 Abacus model used in hardware design 21
3.3 Abacus modification 21
3.4 DE2Interface board 22
3.5 Bead sensor board elevation 22
3.6 Multistage board configuration with respect to 23

abacus bead
3.7 Proximity sensor grid configuration on bead 23

sensor board
3.8 Proximity sensorcontrol circuitry 24
3.9 Configuration of alternate column triggering 25
3.10 Configuration of I2C interconnection 26
3.11 Flowchart for display and two variables 27

arithmetic mode