floating gate based large-scale field-programmable analog arrays

120 Pages·2006·5.31 MB·English

by  Christopher M. Twigg

FLOATING GATE BASED LARGE-SCALE
FIELD-PROGRAMMABLE ANALOG ARRAYS FOR
ANALOG SIGNAL PROCESSING
ADissertation
Presentedto
TheAcademicFaculty
By
ChristopherM.Twigg
InPartialFulfillment
oftheRequirementsfortheDegree
DoctorofPhilosophy
in
ElectricalandComputerEngineering
SchoolofElectricalandComputerEngineering
GeorgiaInstituteofTechnology
August2006
Copyright© 2006byChristopherM.Twigg
FLOATING GATE BASED LARGE-SCALE
FIELD-PROGRAMMABLE ANALOG ARRAYS FOR
ANALOG SIGNAL PROCESSING
Approvedby:
Dr.PaulE.Hasler,Advisor Dr.AaronD.Lanterman
Professor, School ofECE Professor, School ofECE
GeorgiaInstitute ofTechnology GeorgiaInstitute ofTechnology
Atlanta,GA Atlanta,GA
Dr.DavidV.Anderson Dr.MarkT.Smith
Professor, School ofECE Professor, School ofICT
GeorgiaInstitute ofTechnology Swedish RoyalInstitute ofTechnology
Atlanta,GA Kista,Sweden
Dr.JohnB.Peatman
Professor, School ofECE
GeorgiaInstitute ofTechnology
Atlanta,GA
DateApproved: June2006
ACKNOWLEDGMENTS
I would like to thank everyone who helped me along the way from my advisor, Paul
Hasler, to my colleagues within the CADSP research group. I would also like to thank
my friends and family who encouraged me throughoutthe process. However, my greatest
thanks goes to my ever loving wife, Shannon, who has endured many things throughout
my graduate life that I have no doubt caused. I could never have managed through these
lastfewyearswithoutherlove,support,andmostofall,patience.
iii
TABLE OF CONTENTS
ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
LIST OFTABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
LIST OFFIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
CHAPTER1 RECONFIGURABLEANDPROGRAMMABLEANALOG . . 1
1.1 AnalogProcessing,thePastandtheFuture . . . . . . . . . . . . . . . . . 1
1.2 TheFPAA Advantage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 General FPAAArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Large-Scale FPAAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CHAPTER2 FLOATING-GATETRANSISTORS . . . . . . . . . . . . . . . . 8
2.1 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 FloatingGateTransistorArrays . . . . . . . . . . . . . . . . . . . . . . . 15
2.4 SwitchCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5 SwitchProgramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.6 IndirectProgramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.7 ModifiedTunnelingJunctions . . . . . . . . . . . . . . . . . . . . . . . . 24
2.8 ImprovingIsolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CHAPTER3 PROGRAMMABLEVOLTAGE/ CURRENT REFERENCE . . 29
3.1 ArchitectureandTheory . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2 Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3 TemperatureDependence . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4 Long-TermRetention . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CHAPTER4 FIRST GENERATIONFLOATINGGATEFPAA . . . . . . . . 38
4.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.1 CAB ComponentSelection . . . . . . . . . . . . . . . . . . . . . 39
4.1.2 FloatingGateTransistorArrayStructure . . . . . . . . . . . . . . 42
4.2 SynthesizedCircuitsandResults . . . . . . . . . . . . . . . . . . . . . . 43
4.2.1 Follower,Low-PassFilter . . . . . . . . . . . . . . . . . . . . . . 44
4.2.2 Second-Order Section . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2.3 CapacitivelyCoupledCurrent Conveyor . . . . . . . . . . . . . . 47
4.2.4 Third-OrderLadderFilter . . . . . . . . . . . . . . . . . . . . . . 50
4.3 ObservationsandConclusions . . . . . . . . . . . . . . . . . . . . . . . . 52
iv
CHAPTER5 SECOND GENERATIONFLOATINGGATEFPAA . . . . . . . 53
5.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.2 Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3 SynthesizedCircuitsandResults . . . . . . . . . . . . . . . . . . . . . . 59
5.3.1 Follower,Low-PassFilter . . . . . . . . . . . . . . . . . . . . . . 60
5.3.2 CapacitivelyCoupledSummation . . . . . . . . . . . . . . . . . 62
5.3.3 CapacitivelyCoupledDifference . . . . . . . . . . . . . . . . . . 64
5.3.4 ProgrammableSwitchFabricCurrent Source . . . . . . . . . . . 66
5.3.5 ProgrammableVoltageReference . . . . . . . . . . . . . . . . . . 67
5.3.6 EnvelopeDetector . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3.7 Band-PassResonator . . . . . . . . . . . . . . . . . . . . . . . . 71
5.4 ObservationsandConclusions . . . . . . . . . . . . . . . . . . . . . . . . 71
CHAPTER6 HIGHPERFORMANCEFPAA . . . . . . . . . . . . . . . . . . 76
6.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2 Low-PassFilterImplementationandResults . . . . . . . . . . . . . . . . 80
CHAPTER7 LARGE-SCALE FPAAS,THE NEXTGENERATION . . . . . 83
7.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.2 TheChannelSlice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
CHAPTER8 THE FPAAINEDUCATION . . . . . . . . . . . . . . . . . . . . 90
8.1 First-GenerationEducationalFPAABoard . . . . . . . . . . . . . . . . . 91
8.2 Second-GenerationEducationalFPAA Board . . . . . . . . . . . . . . . . 96
8.3 Next-GenerationEducationalFPAA Board . . . . . . . . . . . . . . . . . 100
CHAPTER9 FPAADIRECTIONS . . . . . . . . . . . . . . . . . . . . . . . . 103
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
v
LIST OF TABLES
Table3.1 Reference VoltageDriftData . . . . . . . . . . . . . . . . . . . . . . 36
Table5.1 ExtractedParasiticandDrawnCapacitances. . . . . . . . . . . . . . . 59
vi
LIST OF FIGURES
Figure1.1 DSP power consumption trend compared to power efficient analog
equivalentfunctions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure1.2 Signalprocessinginthereal world. . . . . . . . . . . . . . . . . . . . 2
Figure1.3 ComparisonofcustomanalogICandFPAA designflows. . . . . . . . 3
Figure1.4 GenericFPAAarchitecture. . . . . . . . . . . . . . . . . . . . . . . . 4
Figure1.5 ExampleFPAAswitchandprogrammableelement. . . . . . . . . . . 5
Figure1.6 ExampleFPAAswitchandprogrammableelementusingfloatinggate
transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure2.1 Topviewandcross-sectionlayoutofafloatinggatetransistor. . . . . . 9
Figure2.2 Floatinggatetransistorschematic. . . . . . . . . . . . . . . . . . . . 10
Figure2.3 Gate sweep measurements showing the programmability of floating
gatetransistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure2.4 Conduction band diagram depicting the tunneling process across an
oxide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure2.5 Conduction band diagram depicting hot electron injection across an
nFETchannel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure2.6 Timingdiagramshowingthestepsinvolvedinahotelectroninjection
pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure2.7 Floatinggateinjectionefficiency. . . . . . . . . . . . . . . . . . . . . 14
Figure2.8 Floatinggatetransistorsarrangedintoanarray forprogramming. . . . 15
Figure2.9 Floatinggatetransistorisolationinarrays. . . . . . . . . . . . . . . . 16
Figure2.10 Gatesweepsdepictingthe“on”and“off”statesoffloatinggateswitches. 17
Figure2.11 Comparisonofswitchresistancefor variousdevices. . . . . . . . . . . 18
Figure2.12 Exploitingthesubstratecouplingcapacitorforswitchprogramming. . 21
Figure2.13 Directversusindirectfloatinggatetransistorprogramming. . . . . . . 23
Figure2.14 Layoutforafloatinggatetransistorusingwelltunneling. . . . . . . . 25
Figure2.15 Gatesweepdatashowingwelltunnelingresults. . . . . . . . . . . . . 25
vii
Figure2.16 Layoutforafloatinggatetransistorusingpoly-polycaptunneling. . . 26
Figure2.17 Switchelementusingindirectprogramming. . . . . . . . . . . . . . . 27
Figure2.18 Gatesweepresultsfromtheindirectlyprogrammedswitchtopology. . 28
Figure3.1 Programmablefloatinggatebasedreference. . . . . . . . . . . . . . . 30
Figure3.2 Programmablereference schematicshowingprogrammingswitches. . 32
Figure3.3 Reference programmabilityandaccuracy. . . . . . . . . . . . . . . . . 33
Figure3.4 Reference voltagechangeasafunctionoftemperature. . . . . . . . . 34
Figure3.5 Longtermreference voltagedriftatlowandhightemperatures. . . . . 37
Figure4.1 RASP 1.5diephotograph. . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure4.2 RASP 1.xFPAA architectureandCABcomponents. . . . . . . . . . . 39
Figure4.3 ExampleOTAimplementedusingtransistorswithinanFPAA. . . . . . 40
Figure4.4 RASP 1.xFPAA CABcomponents. . . . . . . . . . . . . . . . . . . . 41
Figure4.5 Floatinggatetransistorarray architectureforprogramming. . . . . . . 42
Figure4.6 G -C low-passfilterimplementedontheRASP 1.5. . . . . . . . . . . 44
M
Figure4.7 FrequencyresponseofG -Clow-passfilter. . . . . . . . . . . . . . . 45
M
Figure4.8 Second-ordersectionimplementedontheRASP 1.5. . . . . . . . . . . 46
Figure4.9 Frequencyresponseofthesecond-ordersectioncircuit. . . . . . . . . 47
Figure4.10 Capacitivelycoupledcurrentconveyor(C4)band-passelement. . . . . 48
Figure4.11 FrequencyresponseoftheC4 band-passelement. . . . . . . . . . . . 49
Figure4.12 Third-orderladdercircuitimplementedontheRASP 1.5. . . . . . . . 50
Figure4.13 Frequencyresponseofthethird-orderladdercircuit. . . . . . . . . . . 51
Figure5.1 RASP 2.7diephotograph. . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure5.2 Thetwo-dimensionalCAB array,RASP 2.xFPAA architecture. . . . . 54
Figure5.3 TheRASP 2.5CAB arraywithrowandcolumnaddressingoffsets. . . 55
Figure5.4 TheRASP 2.7CAB arraywithrowandcolumnaddressingoffsets. . . 55
Figure5.5 SwitchplotdiagramusedtomapcircuitstoFPAACABs. . . . . . . . 57
Figure5.6 Characterizationofdrawncapacitorsandparasiticroutingcapacitance. 59
viii
Figure5.7 Low-passfollowerdatafromtheRASP 2.7. . . . . . . . . . . . . . . 61
Figure5.8 Cornerfrequencyrelationshiptosub-thresholdOTAbiascurrents. . . 61
Figure5.9 AcapacitivelycoupledsummationcircuitusingapFETleakageresis-
tance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure5.10 Summationcircuitidealandmeasuredresults. . . . . . . . . . . . . . 63
Figure5.11 Summationcircuitusingtheswitchfabricasaresistance. . . . . . . . 64
Figure5.12 Capacitivelycoupleddifferencecircuit. . . . . . . . . . . . . . . . . . 65
Figure5.13 Frequencyresponseofthecapacitivedifferenceamplifier. . . . . . . . 65
Figure5.14 Currentsource/reference builtwithinswitchfabric. . . . . . . . . . . 66
Figure5.15 Reference voltageconstructedusingswitchfabriccurrentsource. . . . 67
Figure5.16 Voltagereference characterizationusingavoltagebiasedpFET. . . . . 68
Figure5.17 Voltagereference outputsetbya switchfabriccurrentsource. . . . . . 68
Figure5.18 Synthesizedenvelopedetectorcircuit. . . . . . . . . . . . . . . . . . . 69
Figure5.19 Programmingthesynthesizedenvelopedetector’stimeconstant. . . . . 70
Figure5.20 Measuredminimumdetector’sresponsetovariousfrequencies. . . . . 70
Figure5.21 Synthesizedband-passfilterusinganOTAresonatortopology. . . . . 71
Figure5.22 Switchisolationvariationacrossdie. . . . . . . . . . . . . . . . . . . 72
Figure5.23 Switchisolationbreakpointhistogram. . . . . . . . . . . . . . . . . . 74
Figure6.1 High-performanceFPAAdiephotograph. . . . . . . . . . . . . . . . . 76
Figure6.2 High-performanceFPAAarchitecture. . . . . . . . . . . . . . . . . . 77
Figure6.3 Biquadcircuittopologyusedforthehigh-performanceFPAACAB. . . 78
Figure6.4 Reconfigurabilityinthehigh-performanceFPAAbiquad. . . . . . . . 79
Figure6.5 Low-passfiltersynthesizedusingthebiquadCAB. . . . . . . . . . . . 80
Figure6.6 Biquad synthesized low-pass filter frequency responses for several
loadcapacitances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure7.1 RASP 3.0diephotograph. . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure7.2 Commonalgorithmstepsinaudiosignalprocessing. . . . . . . . . . . 84
ix
Figure7.3 TheRASP 3.0FPAA architecture. . . . . . . . . . . . . . . . . . . . 85
Figure7.4 IndirectlyprogrammeddifferentialswitchusedintheRASP 3.0. . . . 86
Figure7.5 Differentialbiquadcircuittopology. . . . . . . . . . . . . . . . . . . . 87
Figure8.1 EducationallaboratorysetupusingtheRASP 2.5FPAA. . . . . . . . . 91
Figure8.2 Laboratory setup used to prototype and design analog circuits on an
FPAA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure8.3 RASP 2.5FPAA boardinterface commands. . . . . . . . . . . . . . . 93
Figure8.5 CharacterizingapFETusingtheeducationalsetup. . . . . . . . . . . 95
Figure8.6 EducationallaboratorysetupusingtheRASP 2.7FPAA. . . . . . . . . 96
Figure8.7 PortableFPAAlaboratoryinabox. . . . . . . . . . . . . . . . . . . . 97
Figure8.9 Xcircuitschematiccapturetool. . . . . . . . . . . . . . . . . . . . . . 98
Figure8.10 ComparatorcircuitsynthesizedontheRASP 2.7. . . . . . . . . . . . 99
Figure8.11 Results from a simple comparator synthesized using the RASP 2.7
FPAAboard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure8.12 ResultsfromafollowersynthesizedontheRASP 2.7IC. . . . . . . . 101
Figure8.13 FutureeducationallaboratorysetupusingtheplannedRASP 2.8FPAA.101
Figure9.1 RoadmapfortheRASP FPAA andbeyond. . . . . . . . . . . . . . . 103
x