Table Of ContentLecture Notes in Electrical Engineering 231
Forfurthervolumes:
http://www.springer.com/series/7818
Robert Czerwinski and Dariusz Kania
Finite State Machine
Logic Synthesis for
Complex Programmable
Logic Devices
ABC
Authors
RobertCzerwinski DariuszKania
InstituteofElectronics InstituteofElectronics
SilesianUniversityofTechnology SilesianUniversityofTechnology
Gliwice Gliwice
Poland Poland
ISSN1876-1100 e-ISSN1876-1119
ISBN978-3-642-36165-4 e-ISBN978-3-642-36166-1
DOI10.1007/978-3-642-36166-1
SpringerHeidelbergNewYorkDordrechtLondon
LibraryofCongressControlNumber:2012956230
(cid:2)c Springer-VerlagBerlinHeidelberg2013
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Thisis foryou Ewa, Juliaand Filip.Thanks
foralways beingthereforme.
Robert
To Krystyna,Paulina,Michalinaand
Zuzanna.Thankyou verymuchforall.
Dariusz
Preface
ThisbookisamonographdevotedtologicsynthesisandoptimizationforCPLDs.
CPLDs’ macrocells can be individually configured for either sequential or com-
binatorial logic operation. Usually, macrocells consist of three functional blocks:
AND-array, productterm allocator, and programmableregister. The product term
allocator selects how product terms are used. Such a macrocell can also be in-
terpreted as programmable AND-fixed OR structure, well known as PAL-based
(ProgrammableArrayLogic)structure.
Thequestionis:whatshouldbedonewhenthenumberofimplicantsrepresenting
functionexceedsthe numberof producttermsavailable in a logic block? The an-
sweris:theproducttermallocatorshouldallocateextratermsinthemacrocell.Isit
sosimple?Yesandno.Inmanycasessuchasolutionissatisfying.However,prod-
uct terms from neighboring macrocells are utilized. Of course, it would be better
to carryoutlogic synthesisprocessto effectivelyuse the limited numberof prod-
uct terms contained in macrocells. So, the possibilities as well as limitations of
the programmable structures should be considered in the design process as soon
aspossible.
We present logic synthesis and optimization methods dedicated for PAL-based
structures. The methodsstrive to find the optimum fit for the combinationallogic
and finite state machines to the structure of the logic device and aim at area and
speed optimization.The theoreticalbackgroundand completestrategiesare richly
illustrated with examples and figures. This book summarizes many years of our
experienceandthousandsofourexperiments.
We would like to thank Prof. Edward Hrynkiewicz for supporting the creation
ofthebook.AlsowegratefullyacknowledgethehelpfromDr.JozefKulisz.Some
sectionsofthebookwouldnothavebeenwrittenwithouthishelp.Severaldiscus-
sionsonvariousproblemswithourcolleaguesandreviewershavehelpedtoimprove
ourmethods.Wearegratefulforyourhelp.
Gliwice, RobertCzerwinski
January2013 DariuszKania
Contents
1 Introduction.................................................. 1
1.1 ClassicalDesignFlow ..................................... 1
1.2 ProblemFormulation ...................................... 4
1.3 OverviewoftheBook...................................... 5
References.................................................... 6
2 DefinitionsandBasicProperties ................................ 9
2.1 BasicDefinitions.......................................... 9
2.2 FiniteStateMachines ...................................... 11
2.3 PAL-BasedCPLDs ........................................ 12
2.4 TermExpansion........................................... 14
2.5 IntroductiontoTechnology-DependentLogicSynthesis ......... 18
References.................................................... 22
3 SynthesisofFSMs............................................. 25
3.1 IntroductiontoStateAssignment ............................ 25
3.2 ElementsofTwo-LevelMinimization......................... 27
3.3 PrimaryMergingConditions ................................ 28
3.4 SecondaryMergingConditions.............................. 31
3.5 RelationshipbetweenMergingConditions..................... 33
3.6 ImplicantsDistributionTable................................ 36
3.7 OutputLevelActivity ...................................... 39
3.8 ElementsofSymbolicMinimization.......................... 41
3.8.1 StateMinimization.................................. 41
3.8.2 SymbolicImplicantsMinimization .................... 45
3.9 Conclusions .............................................. 47
References.................................................... 47
4 StateAssignmentAlgorithms................................... 49
4.1 AreaOrientedStateAssignment ............................. 49
4.2 SpeedOrientedStateAssignment ............................ 54
4.3 StateAssignmentbyMeansofOutputs ....................... 63
X Contents
4.3.1 MatrixforStateAssignmentbyOutputVectorsMε....... 63
4.3.2 Algorithm ......................................... 66
4.4 Conclusions .............................................. 70
References.................................................... 70
5 AreaOptimizationBasedonGraphsofOutputs .................. 71
5.1 IntroductiontoPAL-OrientedAreaOptimization ............... 71
5.2 GraphofOutputs.......................................... 73
5.3 Area-OrientedOptimizationBasedonGraphofOutputs......... 77
5.4 TheoreticalBackgroundofTechnology-Dependent
Optimization ............................................. 79
5.5 TheAlgorithmofAreaOptimizationBasedonGraphs
ofOutputs ............................................... 80
5.6 Conclusions .............................................. 85
References.................................................... 85
6 SpeedOptimizationUsingTri-stateOutputBuffers ............... 87
6.1 Introduction .............................................. 87
6.2 ProductTermExpansionIdea ............................... 89
6.3 TheoreticalBackgroundsofTechnology-DependedSpeed
OptimizationUsingTri-StateOutputs......................... 92
6.4 AlgorithmofTechnology-DependentSpeedOptimizationof
CombinationalBlock ...................................... 98
6.5 Conclusions .............................................. 103
References.................................................... 103
7 ComplexStrategiesforFSMs................................... 105
7.1 Introduction .............................................. 105
7.2 AreaOptimization......................................... 106
7.3 SpeedOptimization........................................ 112
7.3.1 PAL-OrientedSpeedOptimization..................... 114
7.3.2 UltraFastFSMs .................................... 117
7.4 Conclusions .............................................. 121
References.................................................... 122
8 Experiments.................................................. 123
8.1 Benchmarks.............................................. 123
8.2 ComparisontoAcademicTools.............................. 123
8.2.1 Two-LevelLogicExperiments ........................ 123
8.2.2 SequentialLogicExperiments ........................ 127
8.3 ComparisontoVendorTools ................................ 139
8.3.1 OutputFileFormat.................................. 139
8.3.2 ExperimentalResults................................ 150
8.4 Conclusions .............................................. 157
References.................................................... 158
Contents XI
9 Conclusions .................................................. 161
A FileFormats.................................................. 163
A.1 Benchmarks.............................................. 163
A.2 ESPRESSOFormat........................................ 163
A.3 KISSFormat ............................................. 166
B ESPRESSOMinimizer ........................................ 169
Index ............................................................ 171
Symbols
Booleanspace:
‘1’ logicHIGH
‘0’ logicLOW
Bn n-dimensionBooleanspacewhereB={0,1}
f: Bn→Bm n-input,m-outputfunction
f ith bitofthefunction f; f isalsocalledsingle-outputfunction
i i
fZ logic function that defines state of PAL-based cells with tri-state
x
buffer
μ -range numberofbits‘1’inthevector
ν(A,B) distance between two minterms A and B (the number of bits they
differin)
Δ numberofimplicantsofthefunction f
fi i
x(cid:2)x(cid:3).(cid:4)..(cid:5)x n-elementvector
n
PAL-basedCPLDs:
k numberproducttermsinPAL-basedcell
σ numberofPAL-basedcellsoftheimplementationofthefunction f
f
σ numberoflogiccellsnecessaryforimplementationoftheith func-
fi
tion
σ1 classical implementation of function f – every function has been
f
minimizedseparately
σ numberoflogiccellsnecessarytoimplementtransitiontothestate
Si
S
i
ξ numberofcascadedPAL-basedcellsinthelongestsignalpathfrom
f
theinputstotheoutputs
Z highimpedancestate
Finitestatemachines:
C encodingvector
ε encodingfunction
XIV Symbols
δ transitionfunction
δ ith bitofthetransitionfunction
i
ηSi stateweight(anumberoftransitionstothestateSiofthemachine)
χ chromaticnumber
K minimumnumberofcodebitsinstateassignment
λ outputfunction
λ ith bitoftheoutputfunction
i
ν(S,S ) distance between encoding vectors assigned to states S and S (a
i j i j
numberofbitsofvectorsinwhichtheydiffer)
S finitesetofstates
X finiteinputalphabet
Y finiteoutputalphabet
Mergingconditions:
(cid:6) (cid:7)
S ,S Si primarymergingconditionofatransitionfunction
(cid:6) p r(cid:7)X
λ
S ,S i primarymergingconditionofanoutputfunction
(cid:6) p r(cid:7)X
S ,S Sa,Sb secondarymergingconditioninrespecttopresentstates
(cid:6) p(cid:7) r δi,X
S Sa,Sb secondarymergingconditioninrespecttoinputvectors
p δi,Xu,Xw
GraphofOutputs:
G(Y,U¯) primarygraphofoutputs
Δ (discriminant)thenumberofthesameyvectors
y
μ (Δ ) rangeofΔ discriminant
y y
iΔ discriminants that correspondto the node, which is chosen during
y
ith stepofthetechnology-dependentoptimization
iσ thenumberofPAL-basedlogiccellsnecessarytoimplementmulti-
f
outputimplicantscoupledwithgraphofoutputs
iγ thenumberofPAL-basedlogiccellsnecessarytoimplementinthe
ith steptheimplicantsassociatedwiththenodeofgraph
μ (iΔ )
r y remainder
j
R setofremainders
Math:
== become
card(Y) cardinalityoftheY set
(cid:3)a(cid:4) minimumintegernotlessthana
a≡b (mod n) congruencerelationontheintegers
