Field Programmable Gate Arrays

116 Pages·2017·4.32 MB·English

by  Arto Perttula

Field Programmable Gate
Arrays
TIE-50206 Logic Synthesis
Arto Perttula
Tampere University of Technology
Spring 2017
Outline
• FPGA Architectures
– Logic, interconnects, clocking, integrated macros
– Selection criteria
• Snippets from commercial FPGA architecture:
Stratix III
– Details regarding logic, interconnects etc.
– DRAM interface case study
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References/Acknowledgements
1. The Design Warrior’sGuide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
2. Ari Kulmala, Jouni Tomberg
3. Stratix III Device Handbook
4. Stratix II Device Handbook
– http://www.altera.com/literature/hb/stx2/stratix2_handbook.pdf
5. Quartus II Handbook, Volume 5
– http://www.altera.com/literature/lit-qts.jsp
6. ”Design Guidelinesfor Optimal Resultsin FPGAs”, Jennifer Stephenson, AlteraCorporation
– http://www.altera.com/literature/cp/fpgas-optimal-results-396.pdf
7. V. Betz, FPGAs and StructuredASICs Overview& ResearchChallenges
– http://www.iic.umanitoba.ca/docs/vaughn-betz.ppt
8. Buy FPGA and CPLD Devices, AlteraCorporation, [online] Available:
http://www.altera.com/buy/devices/buy-devices.html
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History
• Firstsimple PLA (Programmable LogicArray) components in 1972
• FirstFPGAs in mid-80s
– AlteraClassic series1984
– Xilinx 2000 series1985
• In 2000s, complete systems are implementablewith FPGAs
1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000
Transistors
ICs (General)
SRAMs & DRAMs
Microprocessors
SPLDs
CPLDs
ASICs
FPGAs
Introduced Actually used 4
a b c
Predefined link
PROM
Programmable link
SPLDs Address 0 & !a&!b&!c
!a&!b& c
Address 1 &
y
!a& b &!c a
Address 2 & arr
!a& b & c R
Address 3 & O
Address 4 & a &!b&!c ble
a
a &!b& c m
Address 5 & m
• First PLDs were PROMs in 1970 a
Address 6 & a & b &!c ogr
a & b & c Pr
Address 7 &
– OR gates were programmable a !a b !b c !c
l l l
• Evolution led to Programmable Predefined AND array w x y
Logic Arrays (PLA) in 1975
PLA
– Both ANDs and Ors programmable a b c
Predefined link
Programmable link
• These are classified as Simple
N/A
& e
Programmable Logic Devices N/A ably
& ma
N/A marr
& graOR
o
a !a b !b c !c l l l Pr
Programmable AND array
w x y
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CPLDs
• Complex Programmable Logic Devices were introduced circa 1980
• Main idea was that majority of the building blocks were not supposed (or could not be) connected
to each other
• Usually everylink is notrequired, somepinsare unidirectional
• Significantsave in interconnectionarea
– => Programmable interconnectionsnonetheless
• Often non-volatile
Programmable
• None/few hard-macros
Interconnect
matrix
SPLD-like
Input/output pins blocks
FPGAs
• Xilinx developed the first in 1984
• The AND- and OR-arrays are replaced by Programmable Logic Blocks
• Containsessentiallya LUT and a flip-flop
• Look-up Table (LUT) implements a truth table
– For example, a 4-input LUT can implement any functionthat has four inputsand one output
a
3-input
b y
LUT
c mux
flip-flop
q
d
clock
reset
A very simple programmable logic block 7
FPGAs #2
• FPGAs can implement vastly more
complex functions than CPLDs
Programmable
interconnect
• It still maintains high configurability and
Programmable
fast design and modification times
logic blocks
• Since the introduction of CPLDs, EDA
tools started to emerge
– Optimal placement of logic functions to
the chip when having only limited number
of links between the functions is far from
trivial
• FPGA devices differ in their
reconfiguration style (we’ll return to this)
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FPGA ARCHITECTURES
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FPGA Basic Logic Cells
LUT
• Include fixed amount of combinational
logic and registers
a) LUT is the prevailing. Flexible.
b) MUX-based structures could do the
trick also
• Usually FPGAs contain 1-4
MUX
programmable registers per logic cells
• In some architectures, the LUTs can
also be used as tiny memory banks
(Xilinx, Altera Stratix III)
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