Employing Multiple CUDA Devices to Accelerate LTL Model Checking

106 Pages·2010·1.3 MB·English

Introduction RedesignofMAP ParallelConstructionofCSR OvercomingMemoryLimitation Experiments Conclusion
Employing Multiple CUDA Devices to Accelerate
LTL Model Checking
Jiˇr´ı Barnat, Petr Bauch, Luboˇs Brim, and Milan Cˇeˇska
FacultyofInformatics,MasarykUniversity
Brno,CzechRepublic
MEMICS2010
basedon
[Barnatetal.ICPADS’10]
23.10, 2010
MilanCˇeˇskaetal. EmployingMultipleCUDADevicestoAccelerateLTLModelChecking 23.10,2010 1/30
Introduction RedesignofMAP ParallelConstructionofCSR OvercomingMemoryLimitation Experiments Conclusion
Motivation
Model Checking
• fully automated approach to the formal verification
• state space explosion problem
• possible solution:
• symbolic representation
• reduction techniques
• platform-dependent verification
DiVinE
• Explicit Parallel LTL Model Checker
• Focuses on full utilization of available HW power
Many-core architectures
• Parallel computing platform of the future?
• Widely accessible due to GP GPU devices
MilanCˇeˇskaetal. EmployingMultipleCUDADevicestoAccelerateLTLModelChecking 23.10,2010 2/30
Introduction RedesignofMAP ParallelConstructionofCSR OvercomingMemoryLimitation Experiments Conclusion
Motivation
Model Checking
• fully automated approach to the formal verification
• state space explosion problem
• possible solution:
• symbolic representation
• reduction techniques
• platform-dependent verification
DiVinE
• Explicit Parallel LTL Model Checker
• Focuses on full utilization of available HW power
Many-core architectures
• Parallel computing platform of the future?
• Widely accessible due to GP GPU devices
MilanCˇeˇskaetal. EmployingMultipleCUDADevicestoAccelerateLTLModelChecking 23.10,2010 2/30
Introduction RedesignofMAP ParallelConstructionofCSR OvercomingMemoryLimitation Experiments Conclusion
Motivation
Model Checking
• fully automated approach to the formal verification
• state space explosion problem
• possible solution:
• symbolic representation
• reduction techniques
• platform-dependent verification
DiVinE
• Explicit Parallel LTL Model Checker
• Focuses on full utilization of available HW power
Many-core architectures
• Parallel computing platform of the future?
• Widely accessible due to GP GPU devices
MilanCˇeˇskaetal. EmployingMultipleCUDADevicestoAccelerateLTLModelChecking 23.10,2010 2/30
Introduction RedesignofMAP ParallelConstructionofCSR OvercomingMemoryLimitation Experiments Conclusion
CUDA Accelerated LTL Model Checking
Acceleration of model checking process by full utilization of
modern massively parallel architectures
• successful redesign of Maximal Accepting Predecessor
algorithm allowing for significant GPU acceleration
[Barnat et al. ICPADS’09].
DiVinE-CUDA
• tool for CUDA Accelerated LTL Model Checking
[Barnat et al. PDMC’09].
Two weaknesses of our approach:
1 expensive phase of encoding the state space into a suitable
and compact representation
2 limited to the middle-size instances that can fit the memory of
a single GPU device
MilanCˇeˇskaetal. EmployingMultipleCUDADevicestoAccelerateLTLModelChecking 23.10,2010 3/30
Introduction RedesignofMAP ParallelConstructionofCSR OvercomingMemoryLimitation Experiments Conclusion
CUDA Accelerated LTL Model Checking
Acceleration of model checking process by full utilization of
modern massively parallel architectures
• successful redesign of Maximal Accepting Predecessor
algorithm allowing for significant GPU acceleration
[Barnat et al. ICPADS’09].
DiVinE-CUDA
• tool for CUDA Accelerated LTL Model Checking
[Barnat et al. PDMC’09].
Two weaknesses of our approach:
1 expensive phase of encoding the state space into a suitable
and compact representation
2 limited to the middle-size instances that can fit the memory of
a single GPU device
MilanCˇeˇskaetal. EmployingMultipleCUDADevicestoAccelerateLTLModelChecking 23.10,2010 3/30
Introduction RedesignofMAP ParallelConstructionofCSR OvercomingMemoryLimitation Experiments Conclusion
CUDA Accelerated LTL Model Checking
Acceleration of model checking process by full utilization of
modern massively parallel architectures
• successful redesign of Maximal Accepting Predecessor
algorithm allowing for significant GPU acceleration
[Barnat et al. ICPADS’09].
DiVinE-CUDA
• tool for CUDA Accelerated LTL Model Checking
[Barnat et al. PDMC’09].
Two weaknesses of our approach:
1 expensive phase of encoding the state space into a suitable
and compact representation
2 limited to the middle-size instances that can fit the memory of
a single GPU device
MilanCˇeˇskaetal. EmployingMultipleCUDADevicestoAccelerateLTLModelChecking 23.10,2010 3/30
Introduction RedesignofMAP ParallelConstructionofCSR OvercomingMemoryLimitation Experiments Conclusion
LTL Model Checking
DoesthemodelM satisfytheformulaϕ?
Inspectedsystem ModelM Formulaϕ Requiredproperty
Model Checker
Yes,Msatisfiesϕ No,Mdoesnotsatisfyϕ
(counterexample)
• required property → formula in Linear Temporal Logic (LTL)
• reduction on accepting cycle detection
MilanCˇeˇskaetal. EmployingMultipleCUDADevicestoAccelerateLTLModelChecking 23.10,2010 4/30
Introduction RedesignofMAP ParallelConstructionofCSR OvercomingMemoryLimitation Experiments Conclusion
Maximal Accepting Predecessor (MAP) Algorithm
Graph corresponding to the state space.
MilanCˇeˇskaetal. EmployingMultipleCUDADevicestoAccelerateLTLModelChecking 23.10,2010 5/30
Introduction RedesignofMAP ParallelConstructionofCSR OvercomingMemoryLimitation Experiments Conclusion
Maximal Accepting Predecessor (MAP) Algorithm
Accepting vertices, accepting cycle.
MilanCˇeˇskaetal. EmployingMultipleCUDADevicestoAccelerateLTLModelChecking 23.10,2010 5/30