Emerging Technology and Architecture for Big-data Analytics

332 Pages·2017·12.35 MB·English

by  Anupam Chattopadhyay, Chip Hong Chang, Hao Yu (eds.)

Anupam Chattopadhyay
Chip Hong Chang
Hao Yu Editors
Emerging
Technology and
Architecture
for Big-data
Analytics
Emerging Technology and Architecture
for Big-data Analytics
Anupam Chattopadhyay • Chip Hong Chang
Hao Yu
Editors
Emerging Technology and
Architecture for Big-data
Analytics
123
Editors
AnupamChattopadhyay ChipHongChang
SchoolofComputerScience SchoolofElectricalandElectronic
andEngineering,SchoolofPhysical Engineering
andMathematicalSciences NanyangTechnologicalUniversity
NanyangTechnologicalUniversity Singapore
Singapore
HaoYu
SchoolofElectricalandElectronic
Engineering
NanyangTechnologicalUniversity
Singapore
ISBN978-3-319-54839-5 ISBN978-3-319-54840-1 (eBook)
DOI10.1007/978-3-319-54840-1
LibraryofCongressControlNumber:2017937358
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Preface
Everyonelovestotalkaboutbigdata,ofcourseforvariousreasons.Wegotintothat
discussionwhenitseemedthatthereisaseriousproblemthatbigdataisthrowing
downtothesystem,architecture,circuitandevendevicespecialists.Theproblemis
ofscale,ofwhicheverydaycomputingexpertswerenotreallyawareof.Thelastbig
waveofcomputingisdrivenbyembeddedsystemsandalltheinfotainmentriding
on top of that. Suddenly, it seemed that people loved to push the envelope of data
anditdoesnotstopgrowingatall.
AccordingtoarecentestimatedonebyCisco® VisualNetworkingIndex(VNI),
global IP traffic crossed the zettabyte threshold in 2016 and grows at a compound
annual growth rate of 22%. Now, zettabyte is 1018 bytes, which is something that
mightnotbeeasilyappreciated.Togiveaneverydaycomparison,takethisestimate.
TheamountofdatathatiscreatedandstoredsomewhereintheInternetis70times
that of the world’s largest library—Library of Congress in Washington DC, USA.
Bigdatais,therefore,aninevitableoutcomeofthetechnologicalprogressofhuman
civilization.Whatliesbeneaththathumongousamountofinformationis,ofcourse,
knowledgethatcouldverymuchmakeorbreakbusinesshouses.Nowonderthatwe
arenowrollingoutcoursecurriculumtotraindatascientists,whoaregearingmore
thanevertolookforaneedleinthehaystack,literally.Thetaskisdifficult,andhere
entersthenewbreedofsystemdesigners,whomighthelptodownsizetheproblem.
The designers’ perspectives that are trickling down from the big data received
considerable attention from top researchers across the world. Upfront, it is the
storage problem that had to be taken care of. Denser and faster memories are
very much needed, as ever. However, big data analytics cannot work on idle data.
Naturally, the next vision is to reexamine the existing hardware platform that
can support intensive data-oriented computing. At the same time, the analysis of
such a huge volume of data needs a scalable hardware solution for both big data
storage and processing, which is beyond the capability of pure software-based
data analytic solutions. The main bottleneck that appeared here is the same one,
knownincomputerarchitecturecommunityforawhile—memorywall.Thereisa
growing mismatch between the access speed and processing speed for data. This
disparity no doubt will affect the big data analytics the hardest. As such, one
v
vi Preface
needs to redesign an energy-efficient hardware platform for future big data-driven
computing. Fortunately, there are novel and promising researches that appeared in
thisdirection.
A big data-driven application also requires high bandwidth with maintained
low-power density. For example, Web-searching application involves crawling,
comparing,ranking,andpagingofbillionsofWebpagesorimageswithextensive
memoryaccess.Themicroprocessorneedstoprocessthestoreddatawithintensive
memoryaccess.Thepresentdatastorageandprocessinghardwarehavewell-known
bandwidthwallduetolimitedaccessingbandwidthatI/Os,butalsopowerwalldue
tolargeleakagepowerinadvancedCMOStechnologywhenholdingdatabycharge.
Assuch,adesignofscalableenergy-efficientbigdataanalytichardwareisahighly
challengingproblem.Itreinforceswell-knownissues,likememoryandpowerwall
that affects the smooth downscaling of current technology nodes. As a result, big
dataanalyticswillhavetolookbeyondthecurrentsolutions—acrossarchitectures,
circuits,andtechnologies—toaddressalltheissuessatisfactorily.
In this book, we attempt to give a glimpse of the things to come. A range
of solutions are appearing that will help a scalable hardware solution based on
the emerging technology (such as nonvolatile memory device) and architecture
(suchasin-memorycomputing)withthecorrespondinglywell-tuneddataanalytics
algorithm(suchasmachinelearning).Toprovideacomprehensiveoverviewinthis
book,wedividedthecontentsintothreemainpartsasfollows:
PartI:State-of-the-ArtArchitecturesandAutomationforDataAnalytics
PartII:NewApproachesandApplicationsforDataAnalytics
PartIII:EmergingTechnology,Circuits,andSystemsforDataAnalytics
As such, this book aims to provide an insight of hardware designs that capture
themostadvancedtechnologicalsolutionstokeeppacewiththegrowingdataand
support the major developments of big data analytics in the real world. Through
thisbook,wetriedourbesttojustifydifferentperspectivesinthegrowingresearch
domain.Naturally,itwouldnotbepossiblewithoutthehardworkfromourexcellent
contributors,whoarewell-establishedresearchersintheirrespectivedomains.Their
chapters, containing state-of-the-art research, provide a wonderful perspective of
howtheresearchisevolvingandwhatpracticalresultsaretobeexpectedinfuture.
Singapore AnupamChattopadhyay
ChipHongChang
HaoYu
Contents
PartI State-of-the-Art Architectures and Automation
forData-Analytics
1 ScalingtheJavaVirtualMachineonaMany-CoreSystem ........... 3
KarthikGanesan,Yao-MinChen,andXiaochenPan
2 AcceleratingDataAnalyticsKernelswithHeterogeneous
Computing................................................................... 25
GuanwenZhong,AlokPrakash,andTulikaMitra
3 Least-squares-solverBasedMachineLearningAccelerator
forReal-timeDataAnalyticsinSmartBuildings....................... 51
HantaoHuangandHaoYu
4 Compute-in-MemoryArchitectureforData-IntensiveKernels....... 77
RobertKaram,SomnathPaul,andSwarupBhunia
5 NewSolutionsforCross-LayerSystem-LevelandHigh-Level
Synthesis..................................................................... 103
WeiZuo,SwathiGurumani,KyleRupnow,andDemingChen
PartII ApproachesandApplicationsforDataAnalytics
6 Side Channel Attacks and Their Low Overhead
CountermeasuresonResidueNumberSystemMultipliers............ 137
GavinXiaoxuYao,MarcStöttinger,RayC.C.Cheung,
andSorinA.Huss
7 Ultra-Low-Power Biomedical Circuit Design
andOptimization:CatchingtheDon’tCares ........................... 159
Xin Li, Ronald D. (Shawn) Blanton, Pulkit Grover,
andDonaldE.Thomas
8 AccelerationofMapReduceFrameworkonaMulticoreProcessor .. 175
LijunZhouandZhiyiYu
vii
viii Contents
9 Adaptive Dynamic Range Compression for Improving
Envelope-BasedSpeechPerception:ImplicationsforCochlear
Implants ..................................................................... 191
Ying-HuiLai,FeiChen,andYuTsao
PartIII Emerging Technology, Circuits and Systems
forData-Analytics
10 NeuromorphicHardwareAccelerationEnabledbyEmerging
Technologies................................................................. 217
ZhengLi,ChenchenLiu,HaiLi,andYiranChen
11 EnergyEfficientSpikingNeuralNetworkDesign
withRRAMDevices........................................................ 245
YuWang,TianqiTang,BoxunLi,LixueXia,andHuazhongYang
12 EfficientNeuromorphicSystemsandEmergingTechnologies:
ProspectsandPerspectives ................................................ 261
AbhronilSengupta,AayushAnkit,andKaushikRoy
13 In-MemoryDataCompressionUsingReRAMs......................... 275
DebjyotiBhattacharjeeandAnupamChattopadhyay
14 BigDataManagementinNeuralImplants:TheNeuromorphic
Approach .................................................................... 293
ArindamBasu,ChenYi,andYaoEnyi
15 DataAnalyticsinQuantumParadigm:AnIntroduction .............. 313
ArpitaMaitra,SubhamoyMaitra,andAsimK.Pal
About the Editors
AnupamChattopadhyay receivedhisBEdegreefromJadavpurUniversity,India,
in 2000. He received his MSc from ALaRI, Switzerland, and PhD from RWTH
Aachen in 2002 and 2008, respectively. From 2008 to 2009, he worked as a
member of consulting staff in CoWare R&D, Noida, India. From 2010 to 2014,
he led the MPSoC Architectures Research Group in UMIC Research Cluster at
RWTH Aachen, Germany, as a junior professor. Since September 2014, he has
been appointed as an assistant professor in the School of Computer Science and
Engineering (SCSE), NTU, Singapore. He also holds adjunct appointment at the
SchoolofPhysicalandMathematicalSciences,NTU,Singapore.
During his PhD, he worked on automatic RTL generation from the architec-
ture description language LISA, which was commercialized later by a leading
EDA vendor. He developed several high-level optimizations and verification flow
for embedded processors. In his doctoral thesis, he proposed a language-based
modeling, exploration, and implementation framework for partially reconfigurable
processors, for which he received outstanding dissertation award from RWTH
Aachen,Germany.
Since 2010, Anupam has mentored more than ten PhD students and numer-
ous master’s/bachelor’s thesis students and several short-term internship projects.
Togetherwithhisdoctoralstudents,heproposeddomain-specifichigh-levelsynthe-
sisforcryptography,high-levelreliabilityestimationflows,generalizationofclassic
linear algebra kernels, and a novel multilayered coarse-grained reconfigurable
architecture.Intheseareas,hepublishedasa(co)authorover100conference/journal
papers, several book chapters for leading press, e.g., Springer, CRC, and Morgan
Kaufmann, and a book with Springer. Anupam served in several TPCs of top
conferences like ACM/IEEE DATE, ASP-DAC, VLSI, VLSI-SoC, and ASAP. He
regularly reviews journal/conference articles for ACM/IEEE DAC, ICCAD, IEEE
TVLSI, IEEE TCAD, IEEE TC, ACM JETC, and ACM TEC; he also reviewed
book proposal from Elsevier and presented multiple invited seminars/tutorials in
prestigiousvenues.HeisamemberofACMandaseniormemberofIEEE.
ix
x AbouttheEditors
Chip HongChang receivedhisBEng(Hons)degreefromtheNationalUniversity
ofSingaporein1989andhisMEngandPhDdegreesfromNanyangTechnological
University (NTU) of Singapore, in 1993 and 1998, respectively. He served as
a technical consultant in the industry prior to joining the School of Electrical
and Electronic Engineering (EEE), NTU, in 1999, where he is currently a tenure
associate professor. He holds joint appointments with the university as assistant
chair of School of EEE from June 2008 to May 2014, deputy director of the 100-
strong Center for High Performance Embedded Systems from February 2000 to
December 2011, and program director of the Center for Integrated Circuits and
SystemsfromApril2003toDecember2009.Hehascoeditedfourbooks,published
10bookchapters,87internationaljournalpapers(ofwhich54arepublishedinthe
IEEETransactions),and158refereedinternationalconferencepapers.Hehasbeen
well recognized for his research contributions in hardware security and trustable
computing, low-power and fault-tolerant computing, residue number systems, and
digitalfilterdesign.Hementoredmorethan20PhDstudents,morethan10MEng
andMScresearchstudents,andnumerousundergraduatestudentprojects.
Dr.ChanghadbeenanassociateeditorfortheIEEETransactionsonCircuitsand
SystemsIfromJanuary2010toDecember2012andhasservedIEEETransactions
on Very Large Scale Integration (VLSI) Systems since 2011, IEEE Access since
March2013,IEEETransactionsonComputer-AidedDesignofIntegratedCircuits
andSystemssince2016,IEEETransactionsonInformationForensicandSecurity
since 2016, Springer Journal of Hardware and System Security since 2016, and
MicroelectronicsJournalsinceMay2014.Hehadbeenaneditorialadvisoryboard
memberoftheOpenElectricalandElectronicEngineeringJournalsince2007and
an editorial board member of the Journal of Electrical and Computer Engineering
since 2008. He also served Integration, the VLSI Journal from 2013 to 2015.
He also guest-edited several journal special issues and served in more than 50
internationalconferences(mostlyIEEE)asadviser,generalchair,generalvicechair,
and technical program cochair and as member of technical program committee.
He is a member of the IEEE Circuits and Systems Society VLSI Systems and
Applications Technical Committee, a senior member of the IEEE, and a fellow of
theIET.
Dr. Hao Yu obtained his BS degree from Fudan University (Shanghai China) in
1999, with 4-year first-prize Guanghua scholarship (top 2) and 1-year Samsung
scholarship for the outstanding student in science and engineering (top 1). After
being selected by mini-CUSPEA program, he spent some time in New York Uni-
versityandobtainedMS/PhDdegreesbothfromelectricalengineeringdepartment
at UCLA in 2007, with major in integrated circuit and embedded computing. He
hasbeenaseniorresearchstaffatBerkeleyDesignAutomation(BDA)since2006,
one of top 100 start-ups selected by Red Herring at Silicon Valley. Since October
2009,hehasbeenanassistantprofessorattheSchoolofElectricalandElectronic
Engineering and also an area director of VIRTUS/VALENS Centre of Excellence,
NanyangTechnologicalUniversity(NTU),Singapore.