Embedded Systems Specification and Design Languages: Selected contributions from FDL’07

267 Pages·2008·3.713 MB·

by  Jens Brandt, Klaus Schneider (auth.), Prof. Eugenio Villar (eds.)

Embedded Systems Specifi cation
and Design Languages
Selected contributions from FDL’07
Lecture Notes in Electrical Engineering
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Eugenio Villar
Editor
Embedded Systems
Specifi cation and Design
Languages
Selected contributions from FDL’07
Editor
Prof. Eugenio Villar
University of Cantabria
Spain
Series Editors
Sio-Iong Ao Li Xu
IAENG Secretariat Zhejiang University
37–39 Hung To Road College of Electrical Engineering
Unit 1, 1/F Department of Systems Science &
Hong Kong Engineering
People’s Republic of China Yu-Quan Campus
310027 Hangzhou
People’s Republic of China
ISBN 978-1-4020-8296-2 e-ISBN 978-1-4020-8297-9
Library of Congress Control Number: 2008921989
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Preface
FDL is the premier European forum to present research results, to exchange
e xperiences, and to learn about new trends in the application of specification and
design languages as well as of associated design and modeling methods and tools
for complex, heterogeneous HW/SW embedded systems. Modeling and s pecification
concepts push the development of new methodologies for design and verification
to system level; thus providing the means for model driven design of complex
information processing systems in a variety of application domains. The aim of
FDL is to cover several related thematic areas and to give an opportunity to gain
up-to-date knowledge in this fast evolving, essential area in system design and
verification.
FDL’07 was the tenth of a series of successful events that were held in Lausanne,
Lyon, Tübingen, Marseille, Frankfurt am Main, Lille and Darmstad. FDL’07 was
held between September 18 and 20, 2007 at the ‘Casa de Convalescència’, the main
Congress facilities of the ‘Universitat Autònoma de Barcelona’ in the city center of
Barcelona, the capital city of Catalonia, Spain.
The high number of submissions to the conference this year allowed the Program
Committee to prepare a high quality conference program.
The book includes a selection of the most relevant contributions based on the
review made by the program committee members and the quality of the contents of
the presentation at the conference. The original content of each paper has been revised
and improved by the authors following the comments made by the reviewers.
FDL’07 was organized again around four thematic areas (TA) that cover
essential aspects of system-level design methods and tools. The book follows the
same structure:
Part I, C/C++ Based System Design, contains seven chapters covering a
comparison between Esterel and SystemC, modeling of asynchronous circuits,
TLM bus models, SystemC debugging, quality analysis of SystemC test
benches and SystemC simulation of a custom configurable architecture.
Part II, Analog, Mixed-Signal, and Heterogeneous System Design, includes
three chapters addressing heterogeneous, mixed-signal modeling, extensions to
VHDL-AMS for partial differential equations and modeling of configurable CMOS
transistors.
v
vi Preface
Part III, UML-Based System Specification and Design, presents six contributions
comparing AADL with MARTE, modeling real-time resources, proposing model trans-
formations to synchronous languages, mapping UML to SystemC, defining a SystemC
UML profile with dynamic features and generating SystemC from StateCharts.
Part IV, Formalisms for Property-Driven Design, is composed of three chapters
presenting methods for monitoring logical and temporal assertions, for transactor-
based formal verification and a case study in property-based synthesis.
The collection of contributions to the book provides an excellent overview of the
latest research contributions to the application of languages to the specification,
design and verification of complex Embedded Systems. The papers cover the most
important aspects in this essential area in Embedded Systems design.
I would like to take this opportunity to thank the member of the program com-
mittee who made a tremendous effort in revising and selecting the best papers
for the conference and the most outstanding among them for this book. Specially,
the four Topic Chairs, Frank Oppenheimer from OFFIS, responsible of C/C++
Based System Design, Sorin Huss from TU Darmstad, responsible of Analog,
Mixed-Signal, and Heterogeneous System Design, Pierre Boulet from Lille
University, responsible of UML-Based System Specification and Design and
Dominique Borrione from TIMA, responsible of Formalisms for Property-
Driven Design. I would like to thank also all the authors for the extra work made
in revising and improving their contributions to the book.
The objective of the book is to serve as a reference text for researchers and
designers interested in the extension and improvement of the application of design
and verification languages in the area of Embedded Systems.
Eugenio Villar
FDL’07 General Chair
University of Cantabria
Contents
Part I C/C++ Based System Design
1 How Different Are Esterel and SystemC . . . . . . . . . . . . . . . . . . . . . . . . 3
Jens Brandt and Klaus Schneider
2 Timed Asynchronous Circuits Modeling and Validation
Using SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Cédric Koch-Hofer and Marc Renaudin
3 On Construction of Cycle Approximate Bus TLMs . . . . . . . . . . . . . . . 31
Martin Radetzki and Rauf Salimi Khaligh
4 Combinatorial Dependencies in Transaction Level Models . . . . . . . . . 45
Robert Guenzel, Wolfgang Klingauf, and James Aldis
5 An Integrated SystemC Debugging Environment . . . . . . . . . . . . . . . . . 59
Frank Rogin, Christian Genz, Rolf Drechsler, and Steffen Rülke
6 Measuring the Quality of a SystemC Testbench
by Using Code Coverage Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Daniel Große, Hernan Peraza, Wolfgang Klingauf, and Rolf Drechsler
7 SystemC-Based Simulation of the MICAS Architecture . . . . . . . . . . . . 87
Dragos Truscan, Kim Sandström, Johan Lilius, and Ivan Porres
Part II Analog, Mixed-Signal, and Heterogeneous System Design
8 Heterogeneous Specifi cation with HetSC and SystemC-AMS:
Widening the Support of MoCs in SystemC . . . . . . . . . . . . . . . . . . . . . . 107
F. Herrera, E. Villar, C. Grimm, M. Damm, and J. Haase
vii
viii Contents
9 An Extension to VHDL-AMS for AMS Systems with Partial
Differential Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Leran Wang, Chenxu Zhao, and Tom J. Kazmierski
10 Mixed-Level Modeling Using Confi gurable MOS
Transistor Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Jürgen Weber, Andreas Lemke, Andreas Lehmler, Mario Anton,
and Sorin A. Huss
Part III UML-Based System Specifi cation and Design
11 Modeling AADL Data Communications with UML MARTE . . . . . . 155
Charles André, Frédéric Mallet, and Robert de Simone
12 Software Real-Time Resource Modeling . . . . . . . . . . . . . . . . . . . . . . . . 169
Frédéric Thomas, Sébastien Gérard, Jérôme Delatour,
and François Terrier
13 Model Transformations from a Data Parallel Formalism
Towards Synchronous Languages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Huafeng Yu, Abdoulaye Gamatié, Eric Rutten, and Jean-Luc Dekeyser
14 UML and SystemC – A Comparison and Mapping Rules
for Automatic Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Per Andersson and Martin Höst
15 An Enhanced SystemC UML Profi le for Modeling
at Transaction-Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
S. Bocchio, E. Riccobene, A. Rosti, and P. Scandurra
16 SC2 StateCharts to SystemC: Automatic Executable
Models Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Marcello Mura and Marco Paolieri
Part IV Formalisms for Property-Driven Design
17 Asynchronous On-Line Monitoring of Logical
and Temporal Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
K. Morin-Allory, L. Fesquet, B. Roustan, and D. Borrione
Contents ix
18 Transactor-Based Formal Verifi cation of Real-Time
Embedded Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
D. Karlsson, P. Eles, and Z. Peng
19 A Case-Study in Property-Based Synthesis: Generating
a Cache Controller from a Property-Set . . . . . . . . . . . . . . . . . . . . . . . . 271
Martin Schickel, Martin Oberkönig, Martin Schweikert,
and Hans Eveking
Chapter 1
How Different Are Esterel and SystemC
Jens Brandt1 and Klaus Schneider2
Abstract In this paper, we compare the underlying models of computation of the
system description languages SystemC and Esterel. Although these languages have
a rather different origin, we show that the execution/simulation of programs written
in these languages consists of many corresponding computation steps. As a conse-
quence, we identify different classes of Esterel programs that can be easily translated
to SystemC processes and vice versa. Moreover, we identify concepts like preemp-
tion in Esterel that are difficult to implement in a structured way in SystemC.
Keywords Synchronous Languages, SystemC, Models of Computation
1.1 Introduction
System description languages like SystemC [11, 13] and synchronous languages
[1, 8] like Esterel [2, 4, 5, 12] are becoming more and more popular for the effi-
cient development of modern hardware-software systems. The common goal of
these languages is to establish a model-based design flow, where different design
tasks like simulation, verification and code generation (for both hardware and
software) can be performed on the basis of a single system description.
While the overall goal of SystemC and Esterel is therefore the same, there are
many differences between these languages. In particular, these languages have
different underlying models of computation.
As a synchronous language, the execution of an Esterel program is divided into
macro steps that correspond with single reactions that are triggered by a common
clock of a hardware circuit. Each macro step is divided into finitely many micro-
steps that are all executed in zero time and within the same variable environment.
1Embedded Systems Group, University of Kaiserslautern, Email: [email protected]
2Embedded Systems Group, University of Kaiserslautern,
Email: [email protected]
E. Villar (ed.) Embedded Systems Specification and Design Languages, 3
© Springer Science + Business Media B.V. 2008