Embedded Software Verification and Debugging

220 Pages·2017·8.813 MB·English

by  Djones Lettnin, Markus Winterholer (eds.)

Embedded Systems
Djones Lettnin
Markus Winterholer E ditors
Embedded
Software
Verification
and Debugging
Embedded Systems
Series editors
Nikil D. Dutt, Irvine, CA, USA
Grant Martin, Santa Clara, CA, USA
Peter Marwedel, Dortmund, Germany
This Series addresses current and future challenges pertaining to embedded
hardware, software, specifications and techniques. Titles in the Series cover a
focusedsetofembeddedtopicsrelatingtotraditionalcomputingdevicesaswellas
high-tech appliances used in newer, personal devices, and related topics. The
material will vary by topic but in general most volumes will include fundamental
material (when appropriate), methods, designs and techniques.
More information about this series at http://www.springer.com/series/8563
Djones Lettnin Markus Winterholer
(cid:129)
Editors
Embedded Software
fi
Veri cation and Debugging
123
Editors
DjonesLettnin Markus Winterholer
Universidade FederaldeSanta Catarina Luzern
Florianópolis Switzerland
Brazil
ISSN 2193-0155 ISSN 2193-0163 (electronic)
Embedded Systems
ISBN978-1-4614-2265-5 ISBN978-1-4614-2266-2 (eBook)
DOI 10.1007/978-1-4614-2266-2
LibraryofCongressControlNumber:2017932782
©SpringerScience+BusinessMedia,LLC2017
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Markus Winterholer dedicates to
Eva-Maria and David.
Djones Lettnin dedicates to
Amelie and Fabiana.
Foreword
I am glad to write a foreword for this book.
Verification(informallydefinedastheprocessoffindingbugsbeforetheyannoy
or kill somebody) is an increasinglyimportant topic. And I amparticularly glad to
see that the book covers the full width of verification, including debugging,
dynamic and formal verification, and assertion creation.
I think that as a field matures, it goes through the following stages regarding
verification:
(cid:129) Trying to pay little attention to it, in an effort to “get things done”;
(cid:129) Then, when bugs start piling up, looking into debugging techniques;
(cid:129) Then, starting to look into more systematic ways offinding new bugs;
(cid:129) And finally, finding a good balance of advanced techniques, such as coverage-
driven dynamic verification, improved assertions, and formal verification.
The area of HW verification (and HW/SW co-verification), where I had the
pleasure of working with Markus, offers an interesting perspective: It has gone
throughall thesestagesyears ago, butitwas never easytoseethefull path ahead.
Consider just the dynamic-verification slice of that history: Initially, no one
could predict how important bugs (and thus verification) would be. It took several
chip-project failures (I personally witnessed one, first hand) to understand that
verification was going to be a big part of our future forever. Then, more random
testing was used. That helped, but not enough, so advanced, constrained-random,
massive test generation was invented. Then, it became clear that functional cov-
erage (not just code coverage) was needed, to make sense of all the resulting runs
and see which covered what.
It then dawned on everybody that this new coverage-driven verification needed
itsownprofessionals,andthus“verificationengineer”asajobdescriptioncameto
be.Then,asCDVstartedproducingmorefailingrunsthanengineerscoulddebug,
emphasis again shifted to advanced debug tools and so on. All of this looks rea-
sonable in hindsight, but was not so obvious on day one.
vii
viii Foreword
Newer fields like autonomous systems are still working their way through the
list,butasthecostofbugstherebecomeclearer,Iexpectthemtoadoptmoreofthe
advanced techniques mentioned in this book.
November 2016 Yoav Hollander
Foretellix Ltd.
Contents
1 An Overview About Debugging and Verification Techniques
for Embedded Software .. ..... .... .... .... .... .... ..... .... 1
Djones Lettnin and Markus Winterholer
1.1 The Importance of Debugging and Verification Processes ... .... 1
1.2 Debugging and Verification Platforms . .... .... .... ..... .... 4
1.2.1 OS Simulation. ..... .... .... .... .... .... ..... .... 4
1.2.2 Virtual Platform .... .... .... .... .... .... ..... .... 5
1.2.3 RTL Simulation .... .... .... .... .... .... ..... .... 5
1.2.4 Acceleration/Emulation .. .... .... .... .... ..... .... 5
1.2.5 FPGA Prototyping .. .... .... .... .... .... ..... .... 6
1.2.6 Prototyping Board .. .... .... .... .... .... ..... .... 6
1.2.7 Choosing the Right Platform for Software
Development and Debugging .. .... .... .... ..... .... 7
1.3 Debugging Methodologies .. .... .... .... .... .... ..... .... 7
1.3.1 Interactive Debugging ... .... .... .... .... ..... .... 8
1.3.2 Post-Process Debugging .. .... .... .... .... ..... .... 8
1.3.3 Choosing the Right Debugging Methodology . ..... .... 10
1.4 Verification Methodologies . .... .... .... .... .... ..... .... 10
1.4.1 Verification Planning .... .... .... .... .... ..... .... 10
1.4.2 Verification Environment Development .. .... ..... .... 11
1.5 Summary .. .... .... ..... .... .... .... .... .... ..... .... 14
References.. .... .... .... ..... .... .... .... .... .... ..... .... 15
2 Embedded Software Debug in Simulation and Emulation
Environments for Interface IP.. .... .... .... .... .... ..... .... 19
Cyprian Wronka and Jan Kotas
2.1 Firmware Debug Methods Overview .. .... .... .... ..... .... 19
2.2 Firmware Debuggability ... .... .... .... .... .... ..... .... 22
2.3 Test-Driven Firmware Development for Interface IP .. ..... .... 24
2.3.1 Starting Development .... .... .... .... .... ..... .... 24
ix
x Contents
2.3.2 First Functional Tests .... .... .... .... .... ..... .... 27
2.3.3 Debugging a System. .... .... .... .... .... ..... .... 31
2.3.4 System Performance .... .... .... .... .... ..... .... 33
2.3.5 Interface IP Performance in a Full Featured OS Case. .... 34
2.3.6 Low Level Firmware Debug in a State-of-the-Art
Embedded System .. .... .... .... .... .... ..... .... 35
2.4 Firmware Bring-up as a Hardware Verification Tool .. ..... .... 35
2.4.1 NAND Flash . ..... .... .... .... .... .... ..... .... 35
2.4.2 xHCI ... .... ..... .... .... .... .... .... ..... .... 36
2.5 Playback Debugging with Cadence® Indago™ Embedded
Software Debugger .. ..... .... .... .... .... .... ..... .... 38
2.5.1 Example . .... ..... .... .... .... .... .... ..... .... 39
2.5.2 Coverage Measurement .. .... .... .... .... ..... .... 42
2.5.3 Drawbacks ... ..... .... .... .... .... .... ..... .... 44
2.6 Conclusions .... .... ..... .... .... .... .... .... ..... .... 44
References . .... .... .... ..... .... .... .... .... .... ..... .... 45
3 The Use of Dynamic Temporal Assertions for Debugging..... .... 47
Ziad A. Al-Sharif, Clinton L. Jeffery and Mahmoud H. Said
3.1 Introduction .... .... ..... .... .... .... .... .... ..... .... 47
3.1.1 DTA Assertions Versus Ordinary Assertions .. ..... .... 48
3.1.2 DTA Assertions Versus Conditional Breakpoints .... .... 50
3.2 Debugging with DTA Assertions .... .... .... .... ..... .... 50
3.3 Design .... .... .... ..... .... .... .... .... .... ..... .... 51
3.3.1 Past-Time DTA Assertions ... .... .... .... ..... .... 53
3.3.2 Future-Time DTA Assertions .. .... .... .... ..... .... 53
3.3.3 All-Time DTA Assertions .... .... .... .... ..... .... 54
3.4 Assertion’s Evaluation ..... .... .... .... .... .... ..... .... 54
3.4.1 Temporal Cycles and Limits... .... .... .... ..... .... 56
3.4.2 Evaluation Log .... .... .... .... .... .... ..... .... 57
3.4.3 DTA Assertions and Atomic Agents .... .... ..... .... 57
3.5 Implementation.. .... ..... .... .... .... .... .... ..... .... 59
3.6 Evaluation.. .... .... ..... .... .... .... .... .... ..... .... 60
3.6.1 Performance .. ..... .... .... .... .... .... ..... .... 61
3.7 Challenges and Future Work .... .... .... .... .... ..... .... 62
3.8 Conclusion .... .... ..... .... .... .... .... .... ..... .... 63
References.. .... .... .... ..... .... .... .... .... .... ..... .... 64
4 Automated Reproduction and Analysis of Bugs in Embedded
Software... .... .... .... ..... .... .... .... .... .... ..... .... 67
Hanno Eichelberger, Thomas Kropf, Jürgen Ruf
and Wolfgang Rosenstiel
4.1 Introduction .... .... ..... .... .... .... .... .... ..... .... 67
4.2 Overview .. .... .... ..... .... .... .... .... .... ..... .... 69