Elastic Bundles: Modelling and Architecting Asynchronous Circuits with Granular Rigidity

217 Pages·2017·2.79 MB·English

Elastic Bundles:
Modelling and Architecting Asynchronous
Circuits with Granular Rigidity
Johnson Fernandes
A Thesis submitted for the degree of Doctor of Philosophy
School of Electrical and Electronic Engineering
Newcastle University
March 2017

Abstract
Integrated Circuit (IC) designs these days are predominantly System-on-Chips (SoCs).
The complexity of designing a SoC has increased rapidly over the years due to growing
process and environmental variations coupled with global clock distribution di(cid:30)culty.
Moreover, traditional synchronous design is not apt to handle the heterogeneous timing
nature of modern SoCs. As a countermeasure, the semiconductor industry witnessed
a strong revival of asynchronous design principles. A new paradigm of digital circuits
emerged, as a result, namely mixed synchronous-asynchronous circuits. With a wave
of recent innovations in synchronous-asynchronous CAD integration, this paradigm is
showing signs of commercial adoption in future SoCs mainly due to the scope for reuse
of synchronous functional blocks and IP cores, and the co-existence of synchronous and
asynchronous design styles in a common EDA framework.
However, there is a lack of formal methods and tools to facilitate mixed synchronous-
asynchronous design. In this thesis, we propose a formal model based on Petri nets with
step semantics to describe these circuits behaviourally. Implication of this model in the
veri(cid:28)cation and synthesis of mixed synchronous-asynchronous circuits is studied. Till
date, this paradigm has been mainly explored on the basis of Globally Asynchronous
Locally Synchronous (GALS) systems. Despite decades of research, GALS design has
failedtogaintractioncommercially. Tounderstanditsdrawbacks,asimulationframework
characterising the physical and functional aspects of GALS SoCs is presented.
Anovelmethodforsynthesisingmixedsynchronous-asynchronouscircuitswithvarying
levels of rigidity is proposed. Starting with a high-level data(cid:29)ow model of a system which
is intrinsically asynchronous, the key idea is to introduce rigidity of chosen granularity
levelsinthemodelwithoutchangingfunctionalbehaviour. Thesystemisthenpartitioned
intofunctionalblocksofsynchronousandasynchronouselementsbeforebeingtransformed
into an equivalent circuit which can be synthesised using standard EDA tools.
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Acknowledgements
I would like to thank my supervisors; Prof. Alex Yakovlev, Dr. Alex Bystrov and Dr.
Danil Sokolov for their invaluable guidance throughout this research. This thesis would
not have been possible without their support, patience and encouragement over the last
(cid:28)ve years.
I would also like to thank Prof. Maciej Koutny and Dr. Marta Pietkiewicz-Koutny
for formalisation of concepts presented in Chapter 4.
Thanks goes to Dr. James Docherty, Dr. Athanasios Grivas, Dr. Graeme Coapes and
Mr. Alessandro De Gennaro for their hours of friendly discussions that kept the research
atmosphere lively.
Special thanks goes to my parents Joseph and Apoline, and to my sisters Jenifer and
Jessica for their love and constant encouragement during the course of this research. I
am also thankful to Ravneet for her patience and wholehearted support, especially during
the writing up of this thesis.
Finally, I would like to acknowledge that this work was partly sponsored by the School
of Electrical and Electronic Engineering, Newcastle University and the EPSRC under the
research grant GAELS EP/I038551/1.
iii

Publications
Parts of this work have appeared in the following publications:
• Journal Paper
(cid:21) J. Fernandes, M. Koutny, L. Mikulski, M. Pietkiewicz-Koutny, D. Sokolov,
and A. Yakovlev, (cid:16)Persistent and Nonviolent steps and the design of GALS
systems(cid:17), Fundamenta Informaticae, vol. 137, pp. 143(cid:21)170, 2015.
• Conference Papers
(cid:21) J. Fernandes, D. Sokolov, and A. Yakovlev, (cid:16)Elastic Bundles: Modelling and
synthesis of asynchronous circuits with granular rigidity(cid:17), International Sym-
posium on Asynchronous Circuits and Systems (ASYNC), 2017. (in press)
(cid:21) J.Fernandes, M.Koutny, M.Pietkiewicz-Koutny, D.Sokolov, andA.Yakovlev,
(cid:16)Step persistence in the design of GALS systems(cid:17), International Conference on
Applications and Theory of Petri Nets and Concurrency (ICATPN), vol. 7927,
pp. 190(cid:21)209, 2013.
• Technical Report
(cid:21) J.Fernandes, M.Koutny, M.Pietkiewicz-Koutny, D.Sokolov, andA.Yakovlev,
(cid:16)Step persistence in the design of GALS systems(cid:17), Technical Report Series, CS-
TR-1349, School of Computing Science, Newcastle University, 2012.
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Contents
Abstract i
Acknowledgements iii
Publications v
List of Figures xiii
List of Tables xiv
List of Abbreviations xv
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Research Goals and Thesis Contribution . . . . . . . . . . . . . . . . . . . 5
1.3 Thesis Organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Background 9
2.1 Behavioural Modelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 Step Transition Systems . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.2 Petri nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Bundled-Data Asynchronous Pipelines . . . . . . . . . . . . . . . . . . . . 14
2.2.1 Synchronous vs. Asynchronous Pipelines . . . . . . . . . . . . . . . 14
2.2.2 Bundled-data protocols . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.3 RT-based Bundled-Data Circuit Synthesis . . . . . . . . . . . . . . 17
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3 Physical Partitioning and its Limitations 21
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.1 Characterising a GALS Design . . . . . . . . . . . . . . . . . . . . . 24
3.2.2 Simulation Framework . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.3 Trade-o(cid:27) Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.4 Tool Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.1 GALS Design Impact to System Latency . . . . . . . . . . . . . . . 40
3.3.2 GALS Design Bene(cid:28)t to System Power . . . . . . . . . . . . . . . . 42
3.3.3 Energy E(cid:30)ciency Analysis . . . . . . . . . . . . . . . . . . . . . . . 45
3.4 Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . 47
4 Theory of Bundles 51
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2 Step Persistence in Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.2.1 De(cid:28)ning Persistent Steps . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.2 Basic Properties of Persistent Steps . . . . . . . . . . . . . . . . . . 58
4.2.3 Global Persistence in Safe pt-nets . . . . . . . . . . . . . . . . . . . 61
4.3 Pruning Reachability Graphs . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.4 Signi(cid:28)cance of Bundles in Digital Circuits . . . . . . . . . . . . . . . . . . 73
4.5 Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . 76
5 Synthesis of Asynchronous Circuits with Granular Rigidity 79
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.2 Modelling Digital Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2.1 PN building blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.2.2 Modelling a Conceptual Design . . . . . . . . . . . . . . . . . . . . 83
5.2.3 Partitioning with Bundles . . . . . . . . . . . . . . . . . . . . . . . 84
5.3 Digital Circuit Synthesis from PN Models . . . . . . . . . . . . . . . . . . 87
5.3.1 Model Transformation to Asynchronous Pipeline Models . . . . . . 87
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