Dual Channel 14-/12-Bit, 250/210 MSPS ADC with DDR LVDS & Parallel CMOS Outputs

84 Pages·2016·2.33 MB·English

ADS62P49 / ADS62P29
ADS62P48 / ADS62P28
www.ti.com SLAS635B–APRIL2009–REVISEDJANUARY2011
Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs
CheckforSamples:ADS62P49/ADS62P29,ADS62P48/ADS62P28
FEATURES • SupportsInputClockAmplitudeDownto400
1
• MaximumSampleRate:250MSPS mVPPDifferential
• 14-BitResolution– ADS62P49/ADS62P48 • InternalandExternalReferenceSupport
• 12-BitResolution– ADS62P29/ADS62P28 • 64-QFNPackage(9mm×9mm)
• TotalPower:1.25Wat250MSPS
ADS62PxxHighSpeedFamily
• DoubleDataRate(DDR)LVDS and Parallel
250MSPS 210MSPS 200MSPS
CMOSOutputOptions
14-BitFamily ADS62P49 ADS62P48
• ProgrammableGainupto6dBforSNR/SFDR
12-BitFamily ADS62P29 ADS62P28
Trade-Off
11-BitFamily ADS62C17
• DCOffsetCorrection
• 90dBCross-Talk
DESCRIPTION
The ADS62Px9/x8 is a family of dual channel 14-bit and 12-bit A/D converters with sampling rates up to 250
MSPS. It combines high dynamic performance and low power consumption in a compact 64 QFN package. This
makesitwell-suitedformulti-carrier,wideband-widthcommunicationsapplications.
The ADS62Px9/x8 has gain options that can be used to improve SFDR performance at lower full-scale input
ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS
(DoubleDataRate)andparallelCMOSdigitaloutput interfacesareavailable.
It includes internal references while the traditional reference pins and associated decoupling capacitors have
been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified
overtheindustrialtemperaturerange(–40°Cto85°C).
Table1.PerformanceSummary
AT170MHZINPUT ADS62P49 ADS62P48 ADS62P29 ADS62P28
0dBgain 75 78 75 78
SFDR,dBc
6dBgain 82 84 82 84
0dBgain 69.8 70.1 68.3 68.7
SINAD,dBFS
6dBgain 66.5 66.3 65.8 65.8
AnalogPower,W 1 0.92 1 0.92
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2009–2011,TexasInstrumentsIncorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarilyincludetestingofallparameters.
ADS62P49 / ADS62P29
ADS62P48 / ADS62P28
SLAS635B–APRIL2009–REVISEDJANUARY2011 www.ti.com
D D
D D D N
D N V G
V G R R
A A D D
LVDSINTERFACE
DA0_P/M
DA2_P/M
DA4_P/M
INA_P Digital
Sample
14-Bit and
and
ADC DDR DA6_P/M
INA_M Hold Serializer
DA8_P/M
DA10_P/M
DA12_P/M
CLKP Output
CLOCKGEN Clock CLKOUTP/M
CLKM
Buffer
DB0_P/M
DB2_P/M
INB_P Digital DB4_P/M
Sample
14-Bit and
and
ADC DDR DB6_P/M
INB_M Hold Serializer
DB8_P/M
DB10_P/M
DB12_P/M
VCM Reference Control Interface
ADS62P49/48 SDOUT
RESET SCLK SEN SDATA CTRL1 CTRL2 CTRL3
B0349-01
Figure1. ADS62P49/48BlockDiagram
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D D
D D D N
D N V G
V G R R
A A D D
LVDSINTERFACE
DA0_P/M
DA2_P/M
DA4_P/M
INA_P Digital
Sample
12-Bit and
and
ADC DDR DA6_P/M
INA_M Hold Serializer
DA8_P/M
DA10_P/M
CLKP Output
CLOCKGEN Clock CLKOUTP/M
CLKM
Buffer
DB0_P/M
DB2_P/M
INB_P Digital DB4_P/M
Sample
12-Bit and
and
ADC DDR DB6_P/M
INB_M Hold Serializer
DB8_P/M
DB10_P/M
VCM Reference Control Interface
ADS62P29/28 SDOUT
RESET SCLK SEN SDATA CTRL1 CTRL2 CTRL3
B0350-01
Figure2. ADS62P29/28BlockDiagram
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PACKAGE/ORDERINGINFORMATION(1)
SPECIFIED
PACKAGE- PACKAGE ECO LEAD/BALL PACKAGE ORDERING TRANSPORT
PRODUCT LEAD DESIGNATOR TEMPERATURE PLAN(2) FINISH MARKING NUMBER MEDIA,QUANTITY
RANGE
ADS62P49IRGCT,
ADS62P49 AZ62P49
ADS62P49IRGCR
TapeandReel
ADS62P48IRGCT,
ADS62P48 GREEN AZ62P48 ADS62P48IRGCR
QFN-64 RGC –40°Cto85°C (RoHSand CuNiPdAu
ADS62P29 noSb/Br) AZ62P29 ADS62P29IRGCT,
ADS62P29IRGCR
TapeandReel
ADS62P28IRGCT,
ADS62P28 AZ62P28
ADS62P28IRGCR
(1) Forthemostcurrentproductandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI
websiteatwww.ti.com.
(2) EcoPlan–Theplannedeco-friendlyclassification:Green(RoHSandnoSb/Br):TIdefines“Green”tomeanPb-Free(RoHScompatible)
andfreeofBromine(Br)andAntimony(Sb)basedflameretardants.
ABSOLUTE MAXIMUM RATINGS(1)
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
VALUE UNIT
Supplyvoltagerange,AVDD –0.3Vto3.9 V
Supplyvoltagerange,DRVDD –0.3Vto2.2 V
VoltagebetweenAGNDandDRGND –0.3to0.3 V
VoltagebetweenAVDDtoDRVDD(AVDDleadsDRVDDduringpower –0.3to4.2 V
up/DRVDDleadsAVDDduringpowerdown)
VoltagebetweenDRVDDtoAVDD(DRVDDleadsAVDDduringpower –2.5to1.7 V
up/AVDDleadsDRVDDduringpowerdown)
Voltageappliedtoexternalpin,VCM(inexternalreferencemode) –0.3to2.0 V
Voltageappliedtoanaloginputpins–INP_A,INM_A,INP_B,INM_B –0.3Vtominimum(3.6,AVDD+0.3V) V
Voltageappliedtoinputpins-CLKP,CLKM(2),RESET,SCLK,SDATA, –0.3VtoAVDD+0.3V V
SEN,CTRL1,CTRL2,CTRL3
T Operatingfree-airtemperaturerange –40to85 °C
A
T Operatingjunctiontemperaturerange 125 °C
J
T Storagetemperaturerange –65to150 °C
stg
ESD,humanbodymodel 2 kV
(1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings
onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating
conditionsisnotimplied.Exposuretoabsolutemaximumratedconditionsforextendedperiodsmayaffectdevicereliability.
(2) WhenAVDDisturnedoff,itisrecommendedtoswitchofftheinputclock(orensurethevoltageonCLKP,CLKMis<|0.3V|).This
preventstheESDprotectiondiodesattheclockinputpinsfromturningon.
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THERMAL INFORMATION
ADS62Pxx
THERMALMETRIC(1) RGCPACKAGE UNITS
64PINS
q Junction-to-ambientthermalresistance(2) 23.0
JA
q Junction-to-case(top)thermalresistance(3) 10.5
JCtop
q Junction-to-boardthermalresistance(4) 4.2
JB
°C/W
y Junction-to-topcharacterizationparameter(5) 0.1
JT
y Junction-to-boardcharacterizationparameter(6) 4.2
JB
q Junction-to-case(bottom)thermalresistance(7) 0.57
JCbot
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953.
(2) Thejunction-to-ambientthermalresistanceundernaturalconvectionisobtainedinasimulationonaJEDEC-standard,high-Kboard,as
specifiedinJESD51-7,inanenvironmentdescribedinJESD51-2a.
(3) Thejunction-to-case(top)thermalresistanceisobtainedbysimulatingacoldplatetestonthepackagetop.Nospecific
JEDEC-standardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88.
(4) Thejunction-to-boardthermalresistanceisobtainedbysimulatinginanenvironmentwitharingcoldplatefixturetocontrolthePCB
temperature,asdescribedinJESD51-8.
(5) Thejunction-to-topcharacterizationparameter,y ,estimatesthejunctiontemperatureofadeviceinarealsystemandisextracted
JT
fromthesimulationdataforobtainingq ,usingaproceduredescribedinJESD51-2a(sections6and7).
JA
(6) Thejunction-to-boardcharacterizationparameter,y ,estimatesthejunctiontemperatureofadeviceinarealsystemandisextracted
JB
fromthesimulationdataforobtainingq ,usingaproceduredescribedinJESD51-2a(sections6and7).
JA
(7) Thejunction-to-case(bottom)thermalresistanceisobtainedbysimulatingacoldplatetestontheexposed(power)pad.Nospecific
JEDECstandardtestexists,butaclosedescriptioncanbefoundintheANSISEMIstandardG30-88.
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RECOMMENDED OPERATING CONDITIONS
MIN TYP MAX UNIT
SUPPLIES
AVDD Analogsupplyvoltage 3.15 3.3 3.6 V
DRVDD Digitalsupplyvoltage 1.7 1.8 1.9 V
ANALOGINPUTS
Differentialinputvoltagerange 2 V
PP
Inputcommon-modevoltage 1.5±0.1 V
VoltageappliedonCMinexternalreferencemode 1.5±0.05 V
Maximumanaloginputfrequencywith2V inputamplitude(1) 500 MHz
pp
Maximumanaloginputfrequencywith1V inputamplitude(1) 800 MHz
pp
CLOCKINPUT
Inputclocksamplerate
Enablelowspeedmode(2) 1 80
ADS62P49/ADS62P29 MSPS
Lowspeedmodedisabled(defaultmodeafterreset) >80 250(3)
Enablelowspeedmode(2) 1 80
ADS62P48/ADS62P28 MSPS
Lowspeedmodedisabled(defaultmodeafterreset) >80 210
Withmultiplexedmodeenabled(4) 1 65 MSPS
Inputclockamplitudedifferential(V –V )(5)(6)
CLKP CLKM
Sinewave,ac-coupled 0.2 1.5 V
PP
LVPECL,ac-coupled 1.6 V
PP
LVDS,ac-coupled 0.7 V
PP
LVCMOS,single-ended,ac-coupled 3.3 V
Inputclockdutycycle 40% 50% 60%
DIGITALOUTPUTS
C MaximumexternalloadcapacitancefromeachoutputpintoDRGND 5 pF
LOAD
R DifferentialloadresistancebetweentheLVDSoutputpairs(LVDSmode) 100 Ω
LOAD
T Operatingfree-airtemperature –40 85 °C
A
(1) SeetheTheoryofOperationsectionforinformation.
(2) Useregisterbit<ENABLELOWSPEEDMODE>,refertotheSerialRegisterMapsectionforinformation.
(3) WithLVDSinterfaceonly;maximumrecommendedsampleratewithCMOSinterfaceis210MSPS.
(4) SeetheMultiplexedOutputModesectionforinformation.
(5) RefertoPerformancevsInputClockAmplitudeChartonFigure35,Figure52,Figure69,andFigure86.
(6) RefertoFigure3forthedefinitionofclockamplitude.
V - V
CLKP CLKM
V
p
0 V
pp
Figure3. ClockAmplitudeDefinitionDiagram
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ELECTRICAL CHARACTERISTICS – ADS62P49/48 and ADS62P29/28
Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,internal
referencemode(unlessotherwisenoted).
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=1.8V
MIN MAX
ADS62P49/ADS62P29 ADS62P48/ADS62P28
PARAMETER 250MSPS 210MSPS UNIT
MIN TYP MAX MIN TYP MAX
ANALOGINPUT
Differentialinputvoltagerange(0dBgain) 2 2 Vpp
Differentialinputresistance(atdc),SeeFigure100 >1 >1 MΩ
Differentialinputcapacitance,SeeFigure101 3.5 3.5 pF
Analoginputbandwidth(with25Ωsourceimpedance) 700 700 MHz
AnalogInputcommonmodecurrent(perchannel) 3.6 3.6 mA/MSPS
VCM Commonmodeoutputvoltage 1.5 1.5 V
VCM Outputcurrentcapability ±4 ±4 mA
DCACCURACY
Offseterror –20 ±2 20 –20 ±2 20 mV
Temperaturecoefficientofoffseterror 0.02 0.02 mV/°C
Variationofoffseterrorwithsupply 0.5 0.5 mV/V
Therearetwosourcesofgainerror–internalreference
inaccuracyandchannelgainerror.
E Gainerrorduetointernalreferenceinaccuracyalone –1 ±0.2 1 –1 ±0.2 1 %FS
GREF
E Gainerrorofchannelalone(1) –1 ±0.2 1 –1 ±0.2 1 %FS
GCHAN
TemperaturecoefficientofE 0.002 0.002 Δ%/°C
GCHAN
Differenceingainerrorsbetweentwochannels
Gain withinthesamedevice –2 2 –2 2
matching %FS
(2) Differenceingainerrorsbetweentwochannels
–4 4 –4 4
acrosstwodevices
POWERSUPPLY
IAVDD Analogsupplycurrent 305 350 280 320 mA
Outputbuffersupplycurrent,LVDSinterfacewith100Ω
IDRVDD 133 175 122 165 mA
externaltermination
Outputbuffersupplycurrent,CMOSinterface,Fin=2MHz,
IDRVDD Noexternalloadcapacitance (3)(4) – 91 mA
Analogpower 1.01 1.15 0.92 1.05 W
Digitalpower,LVDSinterface 0.24 0.315 0.22 0.3 W
Globalpowerdown 45 100 45 100 mW
(1) Thisisspecifiedbydesignandcharacterization;itisnottestedinproduction.
(2) Fortwochannelswithinthesamedevice,onlythechannelgainerrormatters,asthereferenceiscommonforbothchannels.
(3) InCMOSmode,theDRVDDcurrentscaleswiththesamplingfrequency,theloadcapacitanceonoutputpins,inputfrequencyandthe
supplyvoltage(seeFigure92andCMOSinterfacepowerdissipationinapplicationsection).
(4) ThemaximumDRVDDcurrentwithCMOSinterfacedependsontheactualloadcapacitanceonthedigitaloutputlines.Notethatthe
maximumrecommendedloadcapacitanceoneachdigitaloutputlineis10pF.
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ELECTRICAL CHARACTERISTICS – ADS62P49/48
Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,0dBgain,
internalreferencemode(unlessotherwisenoted).
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=1.8V
MIN MAX
ADS62P49 ADS62P48
PARAMETER TESTCONDITIONS 250MSPS 210MSPS UNIT
MIN TYP MAX MIN TYP MAX
Fin=20MHz 73.4 73.4
Fin=60MHz 73 73
SNR Fin=100MHz 72 72
Signaltonoiseratio, dBFS
LVDS 0dBgain 68 71 68 71
Fin=170MHz
6dBgain 66.6 66.4
Fin=230MHz 69.8 69.7
Fin=20MHz 73.2 73
Fin=60MHz 72.7 72.8
SINAD Fin=100MHz 71.2 71.5
Signaltonoiseanddistortionratio, dBFS
LVDS 0dBgain 66.5 69.8 66.5 70.1
Fin=170MHz
6dBgain 66.5 66.3
Fin=230MHz 69 68
ENOB,
Fin=170MHz 11.3 11.4 LSB
Effectivenumberofbits
DNL
Fin=170MHz –0.95 ±0.6 1.3 –0.95 ±0.6 1.3 LSB
Differentialnon-linearity
INL
Fin=170MHz –5 ±2.5 5 –5 ±2.5 5 LSB
Integratednon-linearity
ELECTRICAL CHARACTERISTICS – ADS62P29/28
Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,0dBgain,
internalreferencemode(unlessotherwisenoted).
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=1.8V
MIN MAX
ADS62P29 ADS62P28
PARAMETER TESTCONDITIONS 250MSPS 210MSPS UNIT
MIN TYP MAX MIN TYP MAX
Fin=20MHz 70.7 70.8
Fin=60MHz 70.5 70.6
SNR Fin=100MHz 69.8 70
Signaltonoiseratio, dBFS
LVDS 0dBgain 66.5 69.4 66.5 69.4
Fin=170MHz
6dBgain 66 65.9
Fin=230MHz 68.4 68.4
Fin=20MHz 70.6 70.6
Fin=60MHz 70.3 70.5
SINAD Fin=100MHz 69.3 69.7
Signaltonoiseanddistortionratio, dBFS
LVDS 0dBgain 66 68.3 66 68.7
Fin=170MHz
6dBgain 65.9 65.8
Fin=230MHz 67.9 67.1
ENOB,
Fin=170MHz 11 11.1 LSB
Effectivenumberofbits
DNL
–0.9 ±0.2 1.3 –0.9 ±0.2 1.3 LSB
Differentialnon-linearity
INL
–5 ±1 5 –5 ±1 5 LSB
Integratednon-linearity
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ELECTRICAL CHARACTERISTICS – ADS62P49/48
Typicalvaluesareat25°C,AVDD=3.3V,DRVDD=1.8V,50%clockdutycycle,–1dBFSdifferentialanaloginput,0dBgain,
internalreferencemode(unlessotherwisenoted).
MinandmaxvaluesareacrossthefulltemperaturerangeT =–40°CtoT =85°C,AVDD=3.3V,DRVDD=1.8V
MIN MAX
ADS62P49/ADS62P29 ADS62P48/ADS62P28
PARAMETER TESTCONDITIONS 250MSPS 210MSPS UNIT
MIN TYP MAX MIN TYP MAX
Fin=20MHz 89 85
Fin=60MHz 85 85
SFDR
Fin=100MHz 78 80 dBc
SpuriousFreeDynamicRange
Fin=170MHz 71 75 71 77
Fin=230MHz 77 72
Fin=20MHz 98 98
Fin=60MHz 95 95
SFDR
SpuriousFreeDynamicRange, Fin=100MHz 92 92 dBc
excludingHD2,HD3
Fin=170MHz 77 90 78 91
Fin=230MHz 90 90
Fin=20MHz 93 95
Fin=60MHz 90 94
HD2
Fin=100MHz 90 90 dBc
SecondHarmonicDistortion
Fin=170MHz 71 85 71 88
Fin=230MHz 85 80
Fin=20MHz 89 85
Fin=60MHz 85 85
HD3
Fin=100MHz 78 80 dBc
ThirdHarmonicDistortion
Fin=170MHz 71 75 71 77
Fin=230MHz 77 72
Fin=20MHz 87 83.5
Fin=60MHz 83.5 84.6
THD
Fin=100MHz 77.5 79.7 dBc
Totalharmonicdistortion
Fin=170MHz 70 74 70.5 76.5
Fin=230MHz 75 71
F1=46MHz,F2=50MHz,
87 91
eachtoneat–7dBFS
IMD
2-ToneInter-modulationDistortion F1=185MHz,F2=190 dBFS
MHz, 85 84.5
eachtoneat–7dBFS
Upto200-MHzcross-talk
Cross-talk 90 90 dB
frequency
Recoverytowithin1%(offinal
Clock
Inputoverloadrecovery value)for6-dBoverloadwith 1 1
Cycles
sinewaveinput
PSRR For100-mVppsignalon
25 25 dB
ACPowersupplyrejectionratio AVDDsupply
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DIGITAL CHARACTERISTICS — ADS62Px9/x8
TheDCspecificationsrefertotheconditionwherethedigitaloutputsarenotswitching,butarepermanentlyatavalidlogic
level0or1.AVDD=3.3V,DRVDD=1.8V
ADS62P49/ADS62P48/
PARAMETER TESTCONDITIONS ADS62P29/ADS62P28 UNIT
MIN TYP MAX
DIGITALINPUTS–CTRL1,CTRL2,CTRL3,RESET,SCLK,SDATA,SEN(1)
High-levelinputvoltage Alldigitalinputssupport1.8Vand3.3V 1.3 V
Low-levelinputvoltage CMOSlogiclevels. 0.4 V
SDATA,SCLK(2) 16
High-levelinputcurrent V =3.3V mA
SEN(3) HIGH 10
SDATA,SCLK 0
Low-levelinputcurrent V =0V mA
LOW
SEN –20
Inputcapacitance 4 pF
DIGITALOUTPUTS–CMOSINTERFACE(DA0-DA13,DB0-DB13,CLKOUT,SDOUT)
High-leveloutputvoltage DRVDD
I =1mA DRVDD V
OH –0.1
Low-leveloutputvoltage I =1mA 0 0.1 V
OL
Outputcapacitance(internaltodevice) 2 pF
DIGITALOUTPUTS–LVDSINTERFACE
V High-leveloutputdifferentialvoltage Withexternal100Ωtermination. 275 350 425 mV
ODH
V Low-leveloutputdifferentialvoltage Withexternal100Ωtermination. –425 –350 –275 mV
ODL
V Outputcommon-modevoltage 1 1.15 1.4 V
OCM
Capacitanceinsidethedevicefrom
OutputCapacitance 2 pF
eachoutputtoground
(1) SCLK,SDATA,SENfunctionasdigitalinputpinsinserialconfigurationmode.
(2) SDATA,SCLK,RESET,CTRL1,CTRL2,andCTRL3haveaninternal100-kΩpull-downresistor.
(3) SENhasinternal100kΩpull-upresistortoAVDD.Sincethepull-upisweak,SENcanalsobedrivenby1.8Vor3.3VCMOSbuffers.
DDAnn_PD/DnB+1n_PP
Logic 0 Logic 1
(1) (1)
V =–350 mV V = 350 mV
ODL ODH
DADnnM_D/DnB+n1M_M
V
OCM
V
GGNNDD
T0334-02
(1) Withexternal100-Ωtermination
Figure4. LVDSOutputVoltageLevels
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