DSP Processor Fund Archit Features: Architectures and Features

214 Pages·1997·7.81 MB·English

by  Phil Lapsley

DSP Processor IIFlundamentals
ANOTETOTHEREADER
This bookhas beenelectronicallyreproducedfrom
digital informationstoredatJohnWiley&Sons,Inc.
Wearepleasedthat the use ofthisnewtechnology
will enableustokeepworks ofenduringscholarly
valueinprintaslongasthereisareasonabledemand
forthem. Thecontentofthisbookisidenticalto
previousprintings.
Editorial Board
John B.Anderson, Editor inChief
P.M. Anderson A. H. Haddad P.Laplante
M.Eden R. Herrick R.S.Muller
M. E.El-Hawary G. F.Hoffnagle W.D. Reeve
S. Furui R. F.Hoyte D. J.Wells
S. V.Kartalopoulos
Dudley R. Kay, DirectorofBook Publishing
John Griffin,SeniorAcquisitionsEditor
Karen Hawkins, Editor
LisaDayne, AssistantEditor
LindaMatarazzo, EditorialAssistant
Alsoavailablefrom IEEEPress...
HANDBOOKOFREAL-TIME FASTFOURIERTRANSFORMS:Algorithmsto ProductTesting
Winthrop W.Smith andJoanneM.Smith
1995 Hardcover 496 pp ISBN0-7803-1091-8
ADAIYfEDWAVELETANALYSISFROMTHEORYTOSOFTWARE
CopublishedwithButterworth-Heinemann,Inc.
MladenVictorWicherhauser
1994 Hardcover 504pp ISBN0-56881-041-5
VLSIDIGITALSIGNALPROCESSORS:An Introductionto RapidPrototypingandDesignSynthesis
CopublishedwithAK Peters,Ltd.
VijayK.Madisetti
1995 Hardcover 544pp ISBN0-7806-9406-8
DSP Processor Fundamentals
Architectures and Features
Phil Lapsley
JeffBier
Amit Shoham
BerkeleyDesign Technology, Inc.
Edward A. Lee
University ofCalifornia at Berkeley
+IEEE
TheInstituteofElectrical and Electronics Engineers,lnc.,NewYork
ffiWILEY
~INTERSCIENCE
AJOHNWILEY &SONS, INC.,PUBLICATION
NewYork•Chichester•Weinheim•Brisbane•Singapore •Toronto
No part ofthis publication may be reproduced, stored inaretrieval
system, ortransmitted inany form or byanymeans,electronic,
mechanical, photocopying, recording, scanning orotherwise, except
aspermitted underSections 107and 108ofthe 1976United States
CopyrightAct, withouteitherthe priorwritten permission ofthe
Publisher, or authorization through payment oftheappropriateper
copy feeto the CopyrightClearanceCenter, 222Rosewood Drive,
Danvers, MA 01923, [phone], fax[phone]. Requests
to the Publisherfor permission should beaddressed tothe
Permissions Department, John Wiley & Sons, Inc., 605 Third
Avenue, New York, NY 10158-0012. (212)850-60II,fax (2J2)
850-6008. Evmail: [email protected].
Fororderingand custornerservice,call 1-800-CALL-WILEY.
Wiley-IEEE Press ISBN 0-7803-3405-1
© 1994-1996 by Berkeley DesignTechnology, Inc.
This isthe IEEE reprintingofa book previously published byBerkeley DesignTechnology, Inc.,
39355 CaliforniaStreet, Suite206, Fremont,CA 94538.
[phone]
ISBN 0-7803-3405-1
LibraryofCongress Cataloging-in-PublicationData
DSP processorfundamentals: architectures and features /Phil Lapsley
... [etal.].
Includesindex.
ISBN0-7803-3405-1 (pbk.)
1.Signal processing-Digital techniques-Equipmentand supplies.
2.Microprocessors. I.Lapsley, Phil(date)
TK5102.9.D754 1997
621.382'2'0285416-dc20 96-41738
CIP
To Svend Pedersen, Ira J. Meyer, Yair Shoham,
and Dave Messerschmitt
Contents
Preface xi
Acknowledgments xiii
1. Digital Signal Processing and DSP Systems 1
1.1 Advantages ofDSP 1
1.2 Characteristics ofDSPSystems 2
1.3 Classes of DSPApplications 6
2. DSP Processors, Embodiments, and Alternatives 9
2.1 DSP Processors 9
2.2 DSP ProcessorEmbodiments 12
2.3 Alternatives toCommercialDSPProcessors 18
3. Numeric Representations and Arithmetic 21
3.1 Fixed-PointversusFloating-Point 21
3.2 NativeDataWordWidth 27
3.3 Extended Precision 27
3.4 Floating-PointEmulationand BlockFloating-Point 28
3.5 IEEE-754 Floating-Point 30
3.6 RelationshipbetweenDataWordSizeand Instruction Word Size 30
4. Data Path 31
4.1 Fixed-PointDataPaths 31
4.2 Floating-PointDataPaths 43
4.3 Special FunctionUnits 47
5. Memory Architecture 49
5.1 Memory Structures 51
5.2 FeaturesforReducingMemoryAccess Requirements 55
vii
DSP Processor Fundamentals: Architectures and Features
5.3 Wait States 58
5.4 ROM 60
5.5 External Memory Interiaces 60
5.6 Customization 65
6. Addressing 67
6.1 Implied Addressing 68
6.2 Immediate Data 68
6.3 Memory-Direct Addressing 68
6.4 Register-Direct Addressing 69
6.5 Register-Indirect Addressing 69
6.6 Short Addressing Modes 75
7. Instruction Set 79
7.1 Instruction Types 79
7.2 Registers 84
7.3 Parallel Move Support 86
7.4 Orthogonality 87
7.5 Assembly Language Format 89
8. Execution Control 91
8.1 Hardware Looping 91
8.2 Interrupts 94
8.3 Stacks 98
8.4 Relative Branch Support 98
9. Pipelining 99
9.1 Pipelining and Performance 99
9.2 Pipeline Depth 101
9.3 Interlocking 101
9.4 Branching Effects 104
9.5 Interrupt Effects 106
9.6 Pipeline Programming Models 108
10. Peripherals 111
10.1 Serial Ports 111
10.2 Timers 116
10.3 Parallel Ports 117
viii
Contents
10.4 Bit 1/0 Ports 118
10.5 Host Ports 118
10.6 Communications Ports 118
10.7 On-Chip AID and DIA Converters 119
10.8 External Interrupts 120
10.9 Implications forthe System Designer 120
11. On-Chip Debugging Facilities 121
11.1 Scan-Based Debugging/Emulation Facilities 121
12. Power Consumption and Management 125
12.1 Low-Voltage Operation 125
12.2 Power Management Features 126
13. Clocking 129
14. Price and Packaging 131
14.1 Example Prices 131
14.2 Packaging 132
15. Fabrication Details 135
15.1 Feature Size 135
15.2 Operating Voltage 136
15.3 Die Size 136
16. Development Tools 137
16.1 Assembly Language Tools 137
16.2 High-Level Language Development Tools 152
16.3 Block-Diagram-Based Programming Tools 155
16.4 Real-Time Operating Systems 156
16.5 Multimedia Environments 157
17. Applications Support 159
17.1 Documentation 159
17.2 Applications Engineers 160
17.3 Telephone Support 161
17.4 Bulletin Boards 161
17.5 Training 162
17.6 Third-Party Support 162
ix
DSP Processor Fundamentals: Architectures and Features
18. Conclusions 165
18.1 Choosing a Processor Architecture 165
18.2 DSP Processor Trends 166
Appendix: Vendor Contact Information 171
References and Bibliography 175
Glossary 179
Index 203
About the Authors 209
x