Table Of ContentDigital System Test and Testable Design
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Zainalabedin Navabi
Digital System Test
and Testable Design
Using HDL Models and Architectures
Zainalabedin Navabi
Worcester Polytechnic Institute
Department of Electrical & Computer
Engineering
Worcester, MA
USA
navabi@ece.wpi.edu
ISBN 978-1-4419-7547-8 e-ISBN 978-1-4419-7548-5
DOI 10.1007/978-1-4419-7548-5
Springer New York Dordrecht Heidelberg London
Springer Science+Business Media, LLC 2011
All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the
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Printed on acid-free paper
Springer is part of Springer Science+Business Media (www.springer.com)
This book is dedicated to my wife, Irma, and sons
Aarash and Arvand.
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Preface
This is a book on test and testability of digital circuits in which test is spoken in the language of
design. In this book, the concepts of testing and testability are treated together with digital design
practices and methodologies. We show how testing digital circuits designing testable circuits can
take advantage of some of the well-established RT-level design and verification methodologies and
tools. The book uses Verilog models and testbenches for implementing and explaining fault simula-
tion and test generation algorithms. In the testability part, it describes various scan and BIST meth-
ods in Verilog and uses Verilog testbenches as virtual testers to examine and evaluate these
testability methods. In designing testable circuits, we use Verilog testbenches to evaluate, and thus
improve testability of a design.
The first part of the book develops Verilog test environments that can perform gate-level fault
simulation and test generation. This part uses Verilog PLI along with Verilog’s powerful testbench
development facilities for modeling hardware and programing test environments. The second part
of the book uses Verilog as a hardware design tool for describing DFT and BIST hardware. In this
part, Verilog is used as a hardware description language describing synthesizable testable hardware.
Throughout the book, Verilog simulation helps developing and evaluating test methods and test-
ability hardware constructs.
This book professes a new approach to teaching test. Use of Verilog and Verilog PLI for test
applications is what distinguishes this book from other test and testability books. As HDLs were
used in late 1970s for teaching computer architectures, today, HDLs can be used to illustrate test
methodologies and testability architectures that are otherwise illustrated informally by flow charts,
graphs, and block diagrams. Verilog eliminates ambiguities in test algorithms and BIST and DFT
hardware architectures, and it clearly describes the architecture of the testability hardware and its
test sessions. Describing on-chip test hardware in Verilog helps evaluating the related algorithms in
terms of hardware overhead and timing and thus feasibility of using them on SoC chips. Further
support for this approach comes in use of testbenches. Using PLI in developing testbenches and
virtual testers gives us a powerful programing tool interfaced with hardware described in Verilog.
This mixed hardware/software environment facilitates the description of complex test programs and
test strategies.
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Acknowledgments
When I first thought of using a hardware description language for test purposes, I started using
VHDL models for test purposes in my course on digital system testing at the University of Tehran.
After several years of teaching this course, we switched to Verilog and a set of library components
that facilitated this usage of Verilog was developed. The groups of students who developed the
software and helped me in the formation of the materials are important contributors to this work.
The student, who took the responsibility for the development of the software package was Nastaran
Nemati. She managed the development of the complete library by the time of her graduation in
2010. Her efforts contributed significantly to this work. I thank my students at Worcester Polytechnic
Institute in Massachusetts, USA, and the University of Tehran for sitting at my presentations or
watching them online and making useful suggestions.
When the actual development of the book started, my graduate student, Fatemeh (Negin)
Javaheri, became the key person with whom I discussed my ideas. She was always available for
consulting with me and her ideas helped significantly in shaping the structure of the book. She later
took responsibility for developing the material for the chapter on test compression. Negin continues
to work with me on my research, and she is looking forward to the next book that I want to write.
Another important contributor, also a graduate student at the University of Tehran, is Somayeh
Sadeghi Kohan. Somayeh developed the materials for the chapter on boundary scan, and in the final
stages of this work she was very helpful reviewing chapters and suggesting changes. The feedbacks
she provided and changes she suggested were most helpful. Nastaran Nemati helped developing the
HDL chapter, and Parisa Kabiri and Atie Lotfi also contributed to some of the chapters and helped
reviewing the materials.
As always, and as it is with all my books, Fatemeh Asgari, who has been my assistant for the
past 20 years, became responsible for managing the project. She managed the group of students who
did research, developed software, collected materials, and prepared the final manuscript with its text
and artwork. Fatemeh’s support and management of my writing and research projects have always
been key to the successful completion of these projects. I cannot thank her enough for the work she
has done for me throughout the years.
My work habits and time I spend away from my family working on my research and writing
projects have been particularly difficult for them. However, I have always had their support, under-
standing, and encouragement for all my projects. My wife, Irma, has always been a great help for
me providing an environment that I can spend hours and hours on my writing projects. I thank Irma,
and my sons Aarash and Arvand.
August 2010 Zainalabedin Navabi
navabi@ece.wpi.edu
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