Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission

156 Pages·2019·6.761 MB·English

by  NereoMarkulic,  Kuba Raczkowski,  Jan Craninckx, Piet Wambacq

Analog Circuits and Signal Processing
Nereo Markulic
Kuba Raczkowski
Jan Craninckx
Piet Wambacq
Digital Subsampling
Phase Lock Techniques
for Frequency Synthesis
and Polar Transmission
Analog Circuits and Signal Processing
SeriesEditors:
MohammedIsmail,Dublin,USA
MohamadSawan,Montreal,Canada
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Nereo Markulic (cid:129) Kuba Raczkowski
Jan Craninckx (cid:129) Piet Wambacq
Digital Subsampling Phase
Lock Techniques for
Frequency Synthesis
and Polar Transmission
123
NereoMarkulic KubaRaczkowski
IMEC IMEC
Leuven,Belgium Leuven,Belgium
JanCraninckx PietWambacq
IMEC IMEC
Leuven,Belgium Leuven,Belgium
ISSN1872-082X ISSN2197-1854 (electronic)
AnalogCircuitsandSignalProcessing
ISBN978-3-030-10957-8 ISBN978-3-030-10958-5 (eBook)
https://doi.org/10.1007/978-3-030-10958-5
LibraryofCongressControlNumber:2018966811
©SpringerNatureSwitzerlandAG2019
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Preface
Wireless technology systems have intruded in almost every aspect of today’s
communication.Technologyscalingandinnovationinthefieldofintegratedcircuits
(ICs) nurture this wireless revolution, while the need for higher data throughput
continuestogrow.Thesetrendsunfoldaseverechallenge:intoday’sover-allocated
spectrum,itsefficientusebecomesabsolutelyessential.
In the heart of every transceiver lies a local oscillator (LO), typically imple-
mented as a phase-locked loop (PLL). Crucial aspects of the LO synthesizer
are its phase noise and spurious performance. These impose the fundamental
limitation for efficient transmit and receive modes; hence, a considerable amount
ofenergyandchipareaaretypicallyspenttominimizethem.Moreover,inmodern
systems,thePLLisoftenusedforphasemodulation,withindigitallyintensivepolar
architectures.For spectrallypureandefficientoperation,the digital-to-transmitted
outputconversioncannotbebandwidthlimitedorcompromisedbynonlinearities.
The book starts with an introductive overview of modern frequency synthesis
techniques, delivering the basic operation theory in an intuitive fashion, with
practical implementation in mind. A point of attention is in this context brought
torecentsubsamplingarchitectures.Thesearchitecturesovercometheperformance
boundariestypicallyencounteredinclassicalimplementationsandhavepotentialfor
redefiningtoday’sstateoftheart.Thefollowingchapters,builtaroundthree28nm
bulkCMOSICprototypes,explorethisideaandpresentnew,performance-leading
PLLandpolartransmitterdesigns.
ThefirstpresentedprototypedevelopsanewfractionalPLLfromasubsampling
integer-N frequency multiplier, which in its original form could not be used for
modern wireless standards. To enable fractional modes, while benefiting from
extremelylow-noise subsamplingoperation,we introducethe principleofdigital-
to-timeconverter(DTC)-basedtimedomainsignalprocessing.ADTC,incontrast
to a time-to-digitalconverter (TDC), used in modern digital PLLs, easily reaches
fineresolutionthatiscrucialforspectralpurity.
In the second prototype, we resolve the fundamental limitation of nonlinear
phase-error detection within PLLs. We demonstrate the enhanced, background-
calibratedsubsamplingPLLwhichoperateswitharecord-breaking−247dBfigure
vii
viii Preface
ofmerit, challengingthe mostadvancedart in thefield. The synthesizeris further
expandedintoatwo-pointdigitalphasemodulator,usedasatypicalbuildingblock
forwide-bandpolartransmission.
The third and final IC introduces the digital subsampling polar transmitter
(SSPTX),anewtransmitterarchitecturewhichcombinesthesubsamplingcoreand
anamplitudemodulatingpoweramplifierwithinasinglePLL.Thesystemexhibits
specific features that enable full background cancellation of phase/amplitude
modulation-induceddistortion. The 5.5GHz polar transmitter achieves extremely
accurate performance with −41dB EVM at a 1024 QAM constellation allowing
barrier breaking information throughput, essential for the upcoming wireless
standards.
Leuven,Belgium NereoMarkulic
KubaRaczkowski
PietWambacq
JanCraninckx
Contents
1 Introduction .................................................................. 1
1.1 ATransceiverwithaLocalOscillator(LO)inItsCore............... 1
1.1.1 ACartesianTransceiver........................................ 1
1.1.2 APolarTransmitter............................................. 3
1.2 APhase-LockedLoop(PLL)asanLO................................ 4
1.2.1 FromanAnalogtoaMixed-SignalandDigitalPLL ......... 5
1.2.2 SmallSignalModelofaPLL ................................. 9
1.2.3 PhaseNoiseinPLLs ........................................... 11
1.3 MotivationandResearchObjectives................................... 14
1.3.1 ASubsamplingPLL ........................................... 14
1.3.2 ObjectivesoftheBook ......................................... 17
1.4 BookOutline............................................................ 18
References..................................................................... 19
2 A Digital-to-Time-Converter-BasedSubsampling PLL
forFractionalSynthesis..................................................... 23
2.1 Introduction ............................................................. 23
2.2 Fractional-NOperationofaSubsamplingPLL........................ 25
2.2.1 Time-DomainAnalysisofaSubsamplingPLL............... 25
2.2.2 Enhancementof a SubsamplingPLL to Enable
Fraction-NModeOperation.................................... 25
2.2.3 DigitalModulatorfortheFractional-NSubsamplingPLL... 27
2.3 ImplementationLimitationsandTheirMitigation .................... 28
2.3.1 DTCQuantization .............................................. 28
2.3.2 ADTCVersusaTDCinFractionalFrequencySynthesis.... 30
2.3.3 DTCOffsetandGainError .................................... 30
2.3.4 DTCNonlinearity............................................... 31
2.3.5 DTCPhaseNoise............................................... 32
2.4 CircuitImplementation................................................. 32
2.4.1 ImplementationoftheSubsamplingLoop..................... 34
2.4.2 ImplementationoftheDigital-to-TimeConverter ............ 36
ix
x Contents
2.4.3 ImplementationoftheVCO.................................... 41
2.4.4 ImplementationoftheFrequency-AcquisitionLoop ......... 43
2.5 ExperimentalResults ................................................... 43
2.5.1 MeasuredPhaseNoisePerformance........................... 46
2.5.2 RemainingFractionalSpur..................................... 49
2.5.3 DTC-RelatedMeasurements................................... 49
2.5.4 PerformanceSummaryandComparisontotheState
oftheArt........................................................ 52
2.6 Conclusion .............................................................. 54
References..................................................................... 54
3 A Background-Calibrated Subsampling PLL
forPhase/FrequencyModulation .......................................... 57
3.1 Introduction ............................................................. 57
3.1.1 PLL-BasedPhaseModulation ................................. 57
3.1.2 A DTC-Based Fractional-N Subsampling PLL
forPhaseModulation........................................... 59
3.2 ASelf-CalibratedDTC-BasedFNSSPLL ............................. 60
3.2.1 BasicOperationoftheFNSSPLL.............................. 60
3.2.2 The Random-Jumpfor DTCQuantizationNoise
Randomization.................................................. 62
3.2.3 TheRandom-JumpforDTCNonlinearityRandomization... 64
3.2.4 Self-CalibrationoftheDTCNonlinearity .................... 64
3.2.5 Extractionofthe Current’sSignand Comparator
OffsetCompensation ........................................... 68
3.3 Two-PointPhaseModulatorBasedontheFNSSPLL ................ 70
3.3.1 ModulatingfDACINLCalibration ........................... 71
3.3.2 Delay-SpreadCancellation .................................... 72
3.4 ExperimentalResults ................................................... 74
3.5 Conclusion .............................................................. 81
References..................................................................... 81
4 ABackground-CalibratedDigitalSubsamplingPolarTransmitter.... 85
4.1 Introduction ............................................................. 85
4.2 SystemOverview ....................................................... 86
4.2.1 ADigitalFractional-NSubsamplingPLL..................... 86
4.2.2 Phase/FrequencyandAmplitudeModulation................. 89
4.2.3 PrototypeTargetsandBuildingBlock’sSpecifications ...... 91
4.3 DigitalLinearizationTechniques ...................................... 93
4.3.1 PM-to-PMBackgroundCalibration ........................... 94
4.3.2 AM-to-AMDistortionBackgroundCalibration .............. 96
4.3.3 Phase-DomainMatlabSimulationsofBackground
Calibration ...................................................... 100
4.4 Built-inAM-to-PMDistortionFiltering .............................. 101