Digital Integrated Circuits. Analysis and Design

591 Pages·2010·10.378 MB·English

by  John E. Ayers

S E C O N D E D I T I O N
Digital Integrated
CIRCUITS
Analysis and Design
John E. Ayers
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CRC Press
Taylor & Francis Group
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Boca Raton, FL 33487-2742
© 2010 by Taylor & Francis Group, LLC
CRC Press is an imprint of Taylor & Francis Group, an Informa business
Printed in the United States of America
International Standard Book Number-13: 978-1-4200-6987-7 (Hardcover)
Library of Congress Cataloging-in-Publication Data
Ayers, John E.
Digital integrated circuits : analysis and design / by John E. Ayers. -- 2nd ed.
p. cm.
Includes bibliographical references and index.
ISBN-13: 978-1-4200-6987-7
ISBN-10: 1-4200-6987-X
1. Digital integrated circuits--Design and construction. I. Title.
TK7874.65.A94 2010
621.3815--dc22 2009010227
Visit the Taylor & Francis Web site at
http://www.taylorandfrancis.com
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Contents
Preface .....................................................................................................................xv
About the Author ...............................................................................................xvii
1. Introduction .....................................................................................................1
1.1 Historical Perspective and Moore’s Law .........................................1
1.2 Electrical Properties of Digital Integrated Circuits ........................8
1.2.1 Logic Function ........................................................................9
1.2.2 Static Voltage Transfer Characteristics .............................14
1.2.3 Transient Characteristics ....................................................17
1.2.4 Fan-In and Fan-Out .............................................................20
1.2.5 Dissipation ............................................................................21
1.2.6 Power Delay Product ...........................................................25
1.3 Computer-Aided Design and Verifi cation .....................................25
1.4 Fabrication ..........................................................................................26
1.5 Semiconductors and Junctions ........................................................27
1.6 The MOS Transistor ..........................................................................28
1.7 MOS Gate Circuits ............................................................................29
1.8 Interconnect .......................................................................................30
1.9 Dynamic CMOS ................................................................................31
1.10 Low-Power CMOS .............................................................................31
1.11 Bistable Circuits .................................................................................32
1.12 Memories ............................................................................................33
1.13 Input/Output and Interface Circuits ..............................................33
1.14 Practical Perspective .........................................................................34
1.15 Summary ............................................................................................34
1.16 Exercises ............................................................................................35
References .......................................................................................................38
2. Fabrication ......................................................................................................39
2.1 Introduction .......................................................................................39
2.2 Basic CMOS Fabrication Sequence .................................................39
2.3 Advanced Processing for High-Performance CMOS...................44
2.3.1 Copper Metal ........................................................................45
2.3.2 Metal Gates ...........................................................................48
2.3.3 High-κ Gate Dielectric ........................................................49
2.4 Lithography and Masks ..................................................................50
2.5 Layout and Design Rules .................................................................53
2.5.1 Minimum Line Widths and Spacings ..............................55
2.5.2 Contacts and Vias ................................................................57
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2.6 Testing and Yield ...............................................................................57
2.7 Packaging ...........................................................................................61
2.8 Burn-In and Accelerated Testing ....................................................63
2.9 Practical Perspective .........................................................................63
2.10 Summary ............................................................................................63
2.11 Exercises .............................................................................................64
References .......................................................................................................64
3. Semiconductors and p-n Junctions ...........................................................67
3.1 Introduction .......................................................................................67
3.2 Crystal Structure of Silicon .............................................................67
3.3 Energy Bands .....................................................................................67
3.4 Carrier Concentrations .....................................................................69
3.4.1 Intrinsic Silicon ....................................................................70
3.4.2 n-Type Silicon .......................................................................70
3.4.3 p-Type Silicon .......................................................................72
3.5 Current Transport .............................................................................72
3.6 Carrier Continuity Equations ..........................................................75
3.7 Poisson’s Equation .............................................................................75
3.8 The p-n Junction ................................................................................76
3.8.1 Zero Bias (Thermal Equilibrium) ......................................77
3.8.1.1 Built-In Voltage V ..............................................79
bi
3.8.1.2 Depletion Width W .............................................79
3.8.2 Depletion Capacitance ........................................................80
3.8.3 Forward Bias Current ..........................................................83
3.8.3.1 Short-Base n+-p Junction .....................................85
3.8.3.2 Long-Base n+-p Junction .....................................87
3.8.4 Reverse Bias ..........................................................................87
3.8.5 Reverse Breakdown .............................................................88
3.9 Metal-Semiconductor Junctions ......................................................88
3.10 SPICE Models ....................................................................................90
3.11 Practical Perspective .........................................................................91
3.12 Summary ............................................................................................91
3.13 Exercises .............................................................................................92
References .......................................................................................................93
4. The MOS Transistor .....................................................................................95
4.1 Introduction .......................................................................................95
4.2 The MOS Capacitor ...........................................................................97
4.3 Threshold Voltage ...........................................................................100
4.4 MOSFET Current-Voltage Characteristics ...................................105
4.4.1 Linear Operation ................................................................106
4.4.2 Saturation Operation .........................................................110
4.4.3 Subthreshold Operation ....................................................110
4.4.4 Transit Time ........................................................................114
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4.5 Short-Channel MOSFETs ...............................................................115
4.5.1 The Short-Channel Effect .................................................115
4.5.2 Narrow-Channel Effect .....................................................116
4.5.3 Drain-Induced Barrier Lowering .....................................117
4.5.4 Channel Length Modulation ............................................118
4.5.5 Field-Dependent Mobility and Velocity Saturation ......119
4.5.6 Transit Time in Short-Channel MOSFETs ......................125
4.6 MOSFET Design ..............................................................................126
4.7 MOSFET Capacitances ...................................................................133
4.7.1 Oxide Capacitances ...........................................................134
4.7.2 p-n Junction Capacitances ................................................136
4.7.3 The Miller Effect ................................................................140
4.8 MOSFET Constant-Field Scaling...................................................141
4.9 SPICE MOSFET Models .................................................................142
4.9.1 MOSFET Level 1 Model ....................................................144
4.9.2 Berkeley Short-Channel Insulated Gate Field Effect
Transistor Model ................................................................146
4.9.2.1 BSIM1 Parameters .............................................147
4.9.2.2 BSIM1 Threshold Voltage .................................148
4.9.2.3 BSIM1 Drain Current-Linear Region ..............149
4.9.2.4 BSIM1 Drain Current-Saturation Region .......150
4.9.2.5 BSIM1 Drain Current-Subthreshold
Region .................................................................150
4.9.2.6 Hand Calculations Related to the BSIM1 .......150
4.10 SPICE Demonstrations ...................................................................151
4.11 Practical Perspective .......................................................................156
4.12 Summary ..........................................................................................156
4.13 Exercises ...........................................................................................158
References .....................................................................................................160
5. MOS Gate Circuits .....................................................................................163
5.1 Inverter Static Characteristics .......................................................163
5.2 Critical Voltages ...............................................................................167
5.2.1 Output High-Voltage V .................................................168
OH
5.2.2 Output Low-Voltage V ...................................................168
OL
5.2.3 Input Low-Voltage V .......................................................169
IL
5.2.4 Input High-Voltage V .....................................................170
IH
5.2.5 Switching Threshold (Midpoint) Voltage V .................171
M
5.2 Dissipation .......................................................................................175
5.4 Propagation Delays .........................................................................179
5.5 Fan-Out .............................................................................................182
5.6 NOR Circuits ...................................................................................185
5.7 NAND Circuits ................................................................................186
5.8 Exclusive OR (XOR) Circuit ...........................................................187
5.9 General Logic Design .....................................................................188
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5.10 Pass Transistor Circuits ..................................................................189
5.11 SPICE Demonstrations ...................................................................191
5.12 Practical Perspective .......................................................................195
5.13 Summary ..........................................................................................195
5.14 Exercises ...........................................................................................196
6. Static CMOS ................................................................................................201
6.1 Introduction .....................................................................................201
6.2 Voltage Transfer Characteristic .....................................................201
6.2.1 Voltage Regime One: n-MOS Cutoff and
p-MOS Linear .....................................................................204
6.2.2 Voltage Regime Two: n-MOS Saturated and
p-MOS Linear .....................................................................204
6.2.3 Voltage Regime Three: Both MOSFETs Saturated ........206
6.2.4 Voltage Regime Four: n-MOS Linear and
p-MOS Saturated ................................................................207
6.2.5 Voltage Regime Five: n-MOS Linear and
p-MOS Cutoff .....................................................................208
6.3 Load Surface Analysis ....................................................................210
6.4 Critical Voltages ..............................................................................212
6.4.1 Input Low-Voltage V .......................................................212
IL
6.4.2 Switching Threshold V ...................................................214
M
6.4.3 Input High-Voltage V .....................................................215
IH
6.5 Crossover (Short-Circuit) Current ...............................................216
6.5.1 Current Regime One: n-MOS Cutoff ..............................217
6.5.2 Current Regime Two: n-MOS Saturated .........................217
6.5.3 Current Regime Three: p-MOS Saturated ......................217
6.5.4 Current Regime Four: p-MOS Cutoff ..............................217
6.5.5 Unifi ed Expression for the Crossover Current ..............218
6.5.6 Effect of Threshold Voltages .............................................218
6.6 Propagation Delays .........................................................................222
6.6.1 High-to-Low Propagation Delay t ..............................222
PHL
6.6.2 Low-to-High Propagation Delay t ..............................224
PLH
6.6.3 Propagation Delay Design Equations .............................225
6.6.4 Propagation Delays in the Symmetric Inverter .............225
6.6.5 Approximate Expressions for the Propagation Delays 226
6.6.6 Effect of the Input Rise and Fall Time ............................228
6.7 Inverter Rise and Fall Times ..........................................................230
6.7.1 Fall Time ..............................................................................230
6.7.2 Rise Time .............................................................................232
6.7.3 Effect of the Input Rise and Fall Time on
Output Rise and Fall Time ...............................................234
6.8 Propagation Delays in Short-Channel CMOS .............................236
6.8.1 High-to-Low Propagation Delay t in
PHL
Short-Channel CMOS ........................................................236
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6.8.2 Low-to-High Propagation Delay t in
PLH
Short-Channel CMOS ........................................................237
6.8.3 Comparison of the Short-Channel and
Long-Channel Delay Equations ......................................238
6.8.4 Propagation Delay Design Equations for
Short-Channel CMOS ........................................................239
6.9 Power Dissipation ...........................................................................242
6.9.1 Capacitance Switching Dissipation .................................243
6.9.2 Short-Circuit Dissipation ..................................................244
6.9.3 Leakage Current Dissipation ...........................................245
6.10 Fan-Out .............................................................................................248
6.11 Circuit Delays as Functions of Fan-Out ......................................250
6.12 CMOS Ring Oscillator ....................................................................255
6.13 CMOS Inverter Design ...................................................................255
6.14 CMOS NAND Circuits ...................................................................256
6.14.1 Sizing of Transistors in a CMOS NAND Gate ...............256
6.14.2 Static Characteristics of the CMOS NAND Gate ..........260
6.14.3 Dynamic Characteristics of the CMOS
NAND Gate ........................................................................262
6.15 CMOS NOR Circuits .......................................................................262
6.16 Other Logic Functions in CMOS ..................................................264
6.16.1 Transistor Sizing in CMOS AND-OR-INVERT
Gates ....................................................................................266
6.17 74HC Series CMOS .........................................................................267
6.18 Pseudo NMOS Circuits ..................................................................273
6.19 Scaling of CMOS .............................................................................274
6.19.1 Full Scaling of CMOS ........................................................275
6.19.2 Constant Voltage Scaling of CMOS .................................276
6.20 Latch-Up in CMOS ..........................................................................277
6.21 SPICE Demonstrations ...................................................................278
6.22 Summary ..........................................................................................288
6.23 Practical Perspective .......................................................................289
6.24 Exercises ...........................................................................................289
7. Interconnect .................................................................................................299
7.1 Introduction .....................................................................................299
7.2 Capacitance of Interconnect ..........................................................300
7.3 Resistance of Interconnect .............................................................303
7.4 Inductance of Interconnect ............................................................306
7.5 Modeling Interconnect Delays ......................................................307
7.5.1 Lumped Capacitance Model ............................................307
7.5.2 Distributed Models ............................................................308
7.5.3 Transmission Line Model .................................................310
7.6 Crosstalk ...........................................................................................314
7.7 Polysilicon Interconnect .................................................................317
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7.8 SPICE Demonstrations ...................................................................319
7.9 Practical Perspective .......................................................................326
7.10 Summary ..........................................................................................327
7.11 Exercises ..........................................................................................329
References .....................................................................................................331
8. Dynamic CMOS ..........................................................................................333
8.1 Introduction .....................................................................................333
8.2 Rise Time ..........................................................................................335
8.3 Fall Time ...........................................................................................336
8.4 Charge Sharing ................................................................................339
8.5 Charge Retention ............................................................................340
8.6 Logic Design ....................................................................................343
8.7 Alternative Form Using a p-MOS Pull-Up Network .................345
8.8 Cascading of Dynamic Logic Circuits .........................................346
8.9 Domino Logic ..................................................................................348
8.10 Multiple-Output Domino Logic ....................................................349
8.11 Zipper Logic .....................................................................................351
8.12 Dynamic Pass Transistor Circuits ................................................354
8.12.1 Logic “1” Transfer Delay t ...............................................355
1
8.12.2 Logic “0” Transfer Delay t ...............................................357
0
8.13 CMOS Transmission Gate Circuits ...............................................362
8.14 SPICE Demonstrations ...................................................................364
8.15 Practical Perspective .......................................................................368
8.16 Summary ..........................................................................................368
8.17 Exercises ...........................................................................................369
References .....................................................................................................371
9. Low-Power CMOS ......................................................................................373
9.1 Introduction .....................................................................................373
9.2 Low-Voltage CMOS ........................................................................374
9.3 Multiple Voltage CMOS .................................................................375
9.4 Dynamic Voltage Scaling ...............................................................378
9.5 Active Body Biasing ........................................................................379
9.6 Multiple-Threshold CMOS ............................................................382
9.7 Adiabatic Logic ................................................................................385
9.8 Silicon-on-Insulator .......................................................................388
9.8.1 SOI Technologies: SIMOX and Wafer Bonding ............389
9.8.2 SOI MOSFETs: Fully Depleted or Partially
Depleted ..............................................................................393
9.8.3 SOI for Low-Power CMOS ................................................395
9.9 Practical Perspective .......................................................................397
9.10 Summary ..........................................................................................397
9.11 Exercises ...........................................................................................399
References .....................................................................................................400
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10. Bistable Circuits ..........................................................................................405
10.1 Introduction .....................................................................................405
10.2 Set-Reset Latch .................................................................................408
10.3 SR Flip-Flop ......................................................................................410
10.4 JK Flip-Flops ....................................................................................410
10.5 Other Flip-Flops ..............................................................................415
10.6 Schmitt Triggers ..............................................................................416
10.6.1 CMOS Schmitt Trigger ......................................................419
10.7 SPICE Demonstrations ...................................................................425
10.8 Practical Perspective .......................................................................432
10.9 Summary ..........................................................................................432
10.10 Exercises ...........................................................................................432
References .....................................................................................................434
11. Digital Memories ........................................................................................435
11.1 Introduction .....................................................................................435
11.2 Static Random Access Memory ....................................................437
11.2.1 CMOS SRAM Cell ..............................................................438
11.2.2 NMOS SRAM Cell .............................................................439
11.2.3 SRAM Sense Amplifi ers ...................................................439
11.3 Dynamic Random Access Memory .............................................440
11.4 Read-Only Memory .......................................................................444
11.4.1 NOR Read-Only Memory .................................................444
11.4.2 NAND Read-Only Memory .............................................445
11.5 Programmable Read-Only Memory ............................................447
11.6 Erasable Programmable Read-Only Memory ............................448
11.7 Electrically Erasable Programmable Read-Only Memory ........451
11.8 Flash Memory ..................................................................................453
11.9 Other Nonvolatile Memories .........................................................455
11.10 Access Times in Digital Memories ..............................................459
11.11 Row and Column Decoder Design ...............................................461
11.12 Practical Perspective .......................................................................462
11.13 Summary ..........................................................................................462
11.14 Exercises ...........................................................................................465
References .....................................................................................................466
12. Input/Output and Interface Circuits ......................................................471
12.1 Introduction .....................................................................................471
12.2 Input Electrostatic Discharge Protection .....................................471
12.3 Input Enable Circuits ......................................................................472
12.3.1 CMOS Transmission Gate .................................................473
12.3.1.1 Regime One: n-MOS Linear and
p-MOS Cutoff .....................................................475
12.3.1.2 Regime Two: n-MOS Linear and
p-MOS Linear .....................................................475
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12.3.1.3 Regime Three: n-MOS Cutoff and
p-MOS Linear .....................................................475
12.3.1.4 Overall Characteristic of CMOS
Transmission Gate .............................................476
12.4 CMOS Output Buffers ....................................................................478
12.5 Tri-State Outputs .............................................................................484
12.6 Interface Circuits .............................................................................486
12.6.1 High-Voltage CMOS to Low-Voltage CMOS ..................487
12.6.2 Low-Voltage CMOS to High-Voltage CMOS ..................488
12.7 SPICE Demonstrations ...................................................................489
12.8 Summary ..........................................................................................493
12.9 Practical Perspective .......................................................................497
12.10 Exercises ...........................................................................................497
References .....................................................................................................501
Appendix A List of Symbols ..........................................................................503
Appendix B International System of Units .................................................511
Appendix C Unit Prefi xes ................................................................................513
Appendix D Greek Alphabet .........................................................................515
Appendix E Physical Constants .....................................................................517
Appendix F Properties of Si and Ge at 300 K .............................................519
Appendix G Properties of SiO at 300 K ......................................................521
2
Appendix H Important Equations.................................................................523
Appendix I Design Rules ................................................................................525
Appendix J p-n Junction Switching Transients .........................................535
Appendix K Bipolar and BiCMOS Circuits ................................................539
Appendix L Integrated Circuit Package .......................................................559
Index .....................................................................................................................585
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