Digital Design of Signal Processing Systems: A Practical Approach

608 Pages·2011·7.2 MB·English

by  Shoab Ahmed Khan

DIGITAL DESIGN
KHAN
DIGITAL DESIGN
OF SIGNAL PROCESSING SYSTEMS
A Practical Approach
O D OF SIGNAL PROCESSING SYSTEMS
SHOAB AHMED KHAN
F
National University of Sciences and Technology (NUST), Pakistan

S I
I G
Digital Design of Signal Processing Systems discusses a spectrum of G A Practical Approach
architectures and methods for effective implementation of algorithms in
N
hardware (HW). Encompassing all facets of the subject this book includes
I
conversion of algorithms from floating-point to fixed-point format, parallel A
architectures for basic computational blocks, Verilog Hardware Description T
L
Language (HDL), SystemVerilog and coding guidelines for synthesis.
P A
The book also covers system level design of Multi Processor System on Chip R
(MPSoC); a consideration of different design methodologies including Network O
L
on Chip (NoC) and Kahn Process Network (KPN) based connectivity among
C
processing elements. A special emphasis is placed on implementing streaming
C E
applications such as a digital communication system in HW. Several novel
M architectures for implementing commonly used algorithms in signal processing S D
S
Y are also revealed. With a comprehensive coverage of topics the book provides
I
an appropriate mix of examples to illustrate the design methodology.
CM N E
MY G
CY Key Features: S
S
CMY (cid:31) A practical guide to designing efficient digital systems, covering the Y I
K complete spectrum of digital design from a digital signal processing
S
G
perspective.
T
(cid:31) Provides a full account of HW building blocks and their architectures, while E
also illustrating the effective use of embedded computational resources such M N
as multipliers, adders and memories in FPGAs. SHOAB AHMED KHAN
S
(cid:31) Covers a system level architecture using NoC and KPN for streaming
applications, giving examples of structuring MATLAB® code and its easy
mapping in HW for these applications.
(cid:31) Explains state machine based and Micro-Program architectures with
comprehensive case studies for mapping complex applications.

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DIGITAL DESIGN OF
SIGNAL PROCESSING
SYSTEMS

DIGITAL DESIGN OF
SIGNAL PROCESSING
SYSTEMS
A PRACTICAL APPROACH
Shoab Ahmed Khan
NationalUniversity ofSciences and Technology(NUST), Pakistan
Thiseditionfirstpublished2011
(cid:1)2011JohnWiley&Sons,Ltd
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LibraryofCongressCataloguing-in-PublicationData
Khan,ShoabAhmed.
Digitaldesignofsignalprocessingsystems:apracticalapproach/ShoabAhmedKhan.
p.cm.
Includesbibliographicalreferencesandindex.
ISBN978-0-470-74183-2(cloth)
1. Signalprocessing–Digitaltechniques. I.Title.
TK5102.9.K4842010
621.38202–dc22
2010026285
AcataloguerecordforthisbookisavailablefromtheBritishLibrary.
PrintISBN:9780470741832[HB]
ePDFISBN:9780470974698
oBookISBN:9780470974681
ePubISBN:9780470975251
Setin9.5/11.5ptTimesbyThomsonDigital,Noida,India
Contents
Preface xv
Acknowledgments xix
1 Overview 1
1.1 Introduction 1
1.2 Fueling the Innovation: Moore’s Law 3
1.3 Digital Systems 3
1.3.1 Principles 3
1.3.2 Multi-core Systems 6
1.3.3 NoC-based MPSoC 7
1.4 Examples of Digital Systems 8
1.4.1 Digital Receiver for a Voice Communication System 8
1.4.2 The Backplane of a Router 10
1.5 Components of the Digital Design Process 10
1.5.1 Design 10
1.5.2 Implementation 11
1.5.3 Verification 11
1.6 Competing Objectives in Digital Design 11
1.7 Synchronous Digital Hardware Systems 11
1.8 Design Strategies 12
1.8.1 Example of Design Partitioning 14
1.8.2 NoC-based SoC for Carrier-class VoIP Media Gateway 16
1.8.3 Design Flow Migration 18
References 19
2 Using a Hardware Description Language 21
2.1 Overview 21
2.2 About Verilog 22
2.2.1 History 22
2.2.2 What is Verilog? 22
vi Contents
2.3 System Design Flow 23
2.4 Logic Synthesis 23
2.5 Using the Verilog HDL 24
2.5.1 Modules 24
2.5.2 Design Partitioning 25
2.5.3 Hierarchical Design 26
2.5.4 Logic Values 29
2.5.5 Data Types 30
2.5.6 Variable Declaration 30
2.5.7 Constants 31
2.6 Four Levels of Abstraction 31
2.6.1 Switch Level 32
2.6.2 Gate Level or Structural Modeling 32
2.6.3 Dataflow Level 33
2.6.4 Behavioral Level 39
2.6.5 Verilog Tasks 55
2.6.6 Verilog Functions 56
2.6.7 Signed Arithmetic 56
2.7 Verification in Hardware Design 57
2.7.1 Introduction to Verification 57
2.7.2 Approaches to Testing a Digital Design 58
2.7.3 Levels of Testing in the
Development Cycle 59
2.7.4 Methods for Generating Test Cases 59
2.7.5 Transaction-level Modeling 60
2.8 Example of a Verification Setup 61
2.9 SystemVerilog 61
2.9.1 Data Types 61
2.9.2 Module Instantiation and Port Listing 63
2.9.3 Constructs of the C/C++ Type 64
2.9.4 forand do-whileLoops 65
2.9.5 The alwaysProceduralBlock 65
2.9.6 The finalProceduralBlock 66
2.9.7 The uniqueandpriorityCaseStatements 66
2.9.8 Nested Modules 67
2.9.9 Functions and Tasks 67
2.9.10 The Interface 68
2.9.11 Classes 70
2.9.12 Direct Programming Interface (DPI) 72
2.9.13 Assertion 73
2.9.14 Packages 74
2.9.15 Randomization 74
2.9.16 Coverage 75
Exercises 75
References 80
Contents vii
3 System Design Flow and Fixed-point Arithmetic 81
3.1 Overview 81
3.2 System Design Flow 83
3.2.1 Principles 83
3.2.2 Example:RequirementsandSpecificationsofaUHFSoftware-
defined Radio 85
3.2.3 Coding Guidelines for High-level Behavioral Description 86
3.2.4 Fixed-point versus Floating-point Hardware 88
3.3 Representation of Numbers 89
3.3.1 Types of Representation 89
3.3.2 Two’s Complement Representation 89
3.3.3 Computing Two’s Complement of a Signed Number 90
3.3.4 Scaling 91
3.4 Floating-point Format 92
3.4.1 Normalized and Denormalized Values 93
3.4.2 Floating-point Arithmetic Addition 95
3.4.3 Floating-point Multiplication 96
3.5 Qn.m Format for Fixed-point Arithmetic 96
3.5.1 Introducing Qn.m 96
3.5.2 Floating-point to Fixed-point Conversion of Numbers 97
3.5.3 Addition in Q Format 98
3.5.4 Multiplication in Q Format 98
3.5.5 Bit Growth in Fixed-point Arithmetic 101
3.5.6 Overflow and Saturation 102
3.5.7 Two’s Complement Intermediate Overflow Property 103
3.5.8 Corner Cases 105
3.5.9 Code Conversion and Checking the Corner Case 106
3.5.10 Rounding the Product in Fixed-point Multiplication 107
3.5.11 MATLAB(cid:1) Support for Fixed-point Arithmetic 110
3.5.12 SystemC Support for Fixed-point Arithmetic 111
3.6 Floating-point to Fixed-point Conversion 112
3.7 Block Floating-point Format 113
3.8 Forms of Digital Filter 115
3.8.1 Infinite Impulse Response Filter 115
3.8.2 Quantization of IIR Filter Coefficients 117
3.8.3 Coefficient Quantization Analysis of a Second-order Section 123
3.8.4 Folded FIR Filters 126
3.8.5 Coefficient Quantization of an FIR Filter 127
Exercises 128
References 132
4 Mapping on Fully Dedicated Architecture 133
4.1 Introduction 133
4.2 Discrete Real-time Systems 134
4.3 Synchronous Digital Hardware Systems 136
4.4 Kahn Process Networks 137
viii Contents
4.4.1 Introduction to KPN 137
4.4.2 KPN for Modeling Streaming Applications 139
4.4.3 Limitations of KPN 144
4.4.4 Modified KPN and MPSoC 144
4.4.5 Case Study: GMSK Communication Transmitter 145
4.5 Methods of Representing DSP Systems 148
4.5.1 Introduction 148
4.5.2 Block Diagram 149
4.5.3 Signal Flow Graph 151
4.5.4 Dataflow Graph or Data Dependency Graph 151
4.5.5 Self-timed Firing 156
4.5.6 Single-rate and Multi-rate SDFGs 156
4.5.7 Homogeneous SDFG 158
4.5.8 Cyclo-static DFG 158
4.5.9 Multi-dimensional Arrayed Dataflow Graphs 160
4.5.10 Control Flow Graphs 160
4.5.11 Finite State Machine 161
4.5.12 Transformations on a Dataflow Graph 162
4.5.13 Dataflow Interchange Format (DIF) Language 162
4.6 Performance Measures 162
4.6.1 Iteration Period 162
4.6.2 Sampling Period and Throughput 163
4.6.3 Latency 163
4.6.4 Power Dissipation 164
4.7 Fully Dedicated Architecture 164
4.7.1 The Design Space 164
4.7.2 Pipelining 165
4.7.3 Selecting Basic Building Blocks 167
4.7.4 Extending the Concept of One-to-One Mapping 168
4.8 DFG to HW Synthesis 168
4.8.1 Mapping a Multi-rate DFG in Hardware 169
4.8.2 Centralized Controller for DFG Realization 171
Exercises 173
References 181
5 Design Options for Basic Building Blocks 183
5.1 Introduction 183
5.2 Embedded Processors and Arithmetic Units in FPGAs 183
5.3 Instantiation of Embedded Blocks 186
5.3.1 Example of Optimized Mapping 190
5.3.2 Design Optimization for the Target Technology 192
5.4 Basic Building Blocks: Introduction 194
5.5 Adders 194
5.5.1 Overview 194
5.5.2 Half Adders and Full Adders 195
5.5.3 Ripple Carry Adder 196