Table Of ContentSignals and Communication Technology
Xinpeng Xing
Peng Zhu
Georges Gielen
Design of Power-Efficient
Highly Digital Analog-
to-Digital Converters for
Next-Generation Wireless
Communication Systems
Signals and Communication Technology
More information about this series at http://www.springer.com/series/4748
Xinpeng Xing Peng Zhu
(cid:129)
Georges Gielen
fi
Design of Power-Ef cient
Highly Digital
Analog-to-Digital Converters
for Next-Generation Wireless
Communication Systems
123
Xinpeng Xing Georges Gielen
Graduate Schoolat Shenzhen Departement Elektrotechniek,
TsinghuaUniversity ESAT-MICAS
Shenzhen Katholieke Universiteit Leuven
China Leuven
Belgium
PengZhu
ZhongguancunDongshengTechnologyPark
Analog Devices,Inc.
Beijing
China
ISSN 1860-4862 ISSN 1860-4870 (electronic)
Signals andCommunication Technology
ISBN978-3-319-66564-1 ISBN978-3-319-66565-8 (eBook)
https://doi.org/10.1007/978-3-319-66565-8
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To my wife Qin!
Preface
Mobile devices motivate the continuous development of the communication
industry, meaning low-power designs are in great demand. Analog-to-digital con-
verters(ADCs)buildbridgebetweenanalogfront-endanddigitalcores,andplaya
moreimportantroleinemergingtransceiverarchitectures.Ontheotherhand,dueto
CMOS technology scaling, the ADC design suffers from design issues such as
decreasing headroom voltage. Recently, one popular direction of ADC design is
shiftingmorefunctionsfromthevoltageandtheanalogdomainstothetimeandthe
digital domains, by using a voltage-controlled oscillator (VCO). The implementa-
tion of circuits in the time domain immediately takes advantage again of the
technology scaling with reduced gate delay.
ThisbookisaresultofourresearchworkinESAT-MICAS,K.U.Leuven,inthe
field of highly digital ADC design. Recently, highly digital ADC has drawn more
and more interest from both academy and industry, and the increasing number of
publicationonthistopicisanevidence.Webelievethisisanaturalevolutionwhen
IC designers are facing ongoing-scaling CMOS technologies. With this common
interest,however,wecannotfindsystematicbookonthistopicbutonlypapersand
bookchaptersasfarasweknow.Ithasbeenourmotivationtopresentourworkin
highlydigitalADCasabook.Thiscollectionismainlybasedonourownfivechip
designs in ESAT-MICAS, and also, some previous contributions by various
researchers to this field are also included.
This book focuses on the systematic design of power-efficient highly digital
ADC for future communication applications, with both architecture- and
circuit-levelinnovations.Thefirsttwodesignsare40MHz-BW12bitCTDRADCs
implemented in 90nm CMOS, with quantizations done by highly digital
VCO-based quantizer. Various circuit-level techniques are applied for power
reduction, including the shaped switched capacitor digital-to-analog converter (SC
DAC), the look-up-table (LUT)-based digital calibration, and the current-sharing
feedforward-compensated OTA. The third design is a 40MHz-BW two-step
open-loop VCO-based ADC in 40nm CMOS. With hardware-economic structure
and mostly digital building blocks, an excellent FoM of 42fJ/step is obtained.
However,onlyfirst-ordernoiseshapingisrealized forthewholeADC,limitingits
vii
viii Preface
SNR performance. To go further, in our fourth design, a nonlinearity cancellation
0–2MASHDRADCstructurewithinnovativedual-inputVCO-basedquantizeris
adopted. The optimized systematic parameters and the highly digital circuit blocks
extendtheFoMofthestate-of-the-arthigh-bandwidthDRADCsto35fJ/step.With
second-order noise shaping, the ADC performance is improved, and one analog
front-end integrator is still needed, however. In the final design of this work, a
VCO-basedintegratorisproposedtoreplacethepower-hungryanalogintegratorin
the traditional DR ADC topology, realizing second-order DR ADC without any
analog integrator. 74-dB SFDR and a FoM of 52fJ/step over a 40MHz bandwidth
have been achieved in the demonstration.
With the state-of-the-art power efficiencies, the presented highly digital ADCs
are very suitable for the applications of next-generation wireless communication
standards, including but not limited to 802.11n and LTE. Furthermore, the design
methodologyanddesigninnovationsdescribedinthisbookcouldalsobeappliedto
ADCs for other applications.
Shenzhen, China Xinpeng Xing
Beijing, China Peng Zhu
Leuven, Belgium Georges Gielen
March 2017
Acknowledgements
At the moment to archive our work, we could not forget the people, who con-
tributed directly or indirectly to this book. First, we would like to thank editor
Oliver Jackson, Springer UK, for his careful and patient organization work during
the whole publication procedure. We also would like to express our gratitude to
anonymous reviewers for their valuable comments and suggestions for improve-
ment. During our PhDs in K.U. Leuven, Prof. Jean Berlamont, Prof. Michiel
Steyaert, Prof. Marc Moonen, Prof. Wim Dehaene, Prof. Pieter Rombouts, Prof.
Patrick Wollants, Prof. Guy Vandenbosch, all in K.U. Leuven, and Prof. Michael
Peter Kennedy, University College Cork, and Andrea Baschirotto, University of
Milano-Bicoccaservedkindlyastheprogramcommitteemembers,manythanksto
themfortheirvaluablefeedbackandcommunicationsonourwork.Wewouldlike
to thank Danielle Vermetten, Ben Geeraerts, Chris Mertens, Frederik Daenen,
Noella Gaethofs, and Michel De Cooman in MICAS-ESAT for their outstanding
secretariat and logistic works. Without their supports, we cannot accomplish the
wholechipdesign.Wealsowouldliketothankourex-colleagues(alsofriends)Yi
Ke and Peng Gao for the technical discussion in data converters and so on.
Besides,wewouldliketoconveyourthankstotheFundsforScientificResearch
Flanders (FWO-V.), Belgium, and the European Union Seventh Framework
Programme for Research and Technology Development (EU-FP7) for the project
financial supports.
Finally, our most grateful thanks are for our families, for their invaluable love,
support, and patience. Also many thanks to our colleagues and friends, for the
wonderful time and memory in Leuven.
Shenzhen, China Xinpeng Xang
March 2017
ix
Contents
1 Introduction.... .... .... ..... .... .... .... .... .... ..... .... 1
1.1 Background and Motivation. .... .... .... .... .... ..... .... 1
1.1.1 Communication Evolution. .... .... .... .... ..... .... 1
1.1.2 CMOS Technology.. .... .... .... .... .... ..... .... 3
1.1.3 Wireless Receiver Architectures .... .... .... ..... .... 6
1.2 The Research Objective of the Book .. .... .... .... ..... .... 8
1.3 The Book Organization .... .... .... .... .... .... ..... .... 9
References.. .... .... .... ..... .... .... .... .... .... ..... .... 10
2 A/D Converters and Applications.... .... .... .... .... ..... .... 13
2.1 Introduction .... .... ..... .... .... .... .... .... ..... .... 13
2.2 ADC Specifications .. ..... .... .... .... .... .... ..... .... 14
2.2.1 ADC Speed... ..... .... .... .... .... .... ..... .... 14
2.2.2 ADC Accuracy ..... .... .... .... .... .... ..... .... 14
2.2.3 ADC FoM.... ..... .... .... .... .... .... ..... .... 16
2.3 ADC Architectures... ..... .... .... .... .... .... ..... .... 16
2.3.1 Flash ADC ... ..... .... .... .... .... .... ..... .... 19
2.3.2 Two-Step ADC..... .... .... .... .... .... ..... .... 21
2.3.3 Pipelined ADC ..... .... .... .... .... .... ..... .... 22
2.3.4 SAR ADC.... ..... .... .... .... .... .... ..... .... 23
2.3.5 Delta-Sigma ADC... .... .... .... .... .... ..... .... 24
2.3.6 ADC Architecture Summmary and Comparison ..... .... 26
2.4 Application of ADC in Communications ... .... .... ..... .... 28
2.5 Conclusions .... .... ..... .... .... .... .... .... ..... .... 33
References.. .... .... .... ..... .... .... .... .... .... ..... .... 34
3 Continuous-Time Delta-Sigma Modulators .... .... .... ..... .... 37
3.1 Introduction .... .... ..... .... .... .... .... .... ..... .... 37
3.2 DSM Basics: Oversampling and Noise-Shaping.. .... ..... .... 38
3.3 DSM Structures . .... ..... .... .... .... .... .... ..... .... 41
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