Design of Analog Integrated Circuits Using Simulated Annealing/Quenching with Crossovers and ...

26 Pages·2012·0.84 MB·English

ChCahpatpetre r110
Design of Analog Integrated Circuits Using
Simulated Annealing/Quenching with Crossovers
and Particle Swarm Optimization
TiagoOliveiraWeberandWilhelmusA.M.VanNoije
Additionalinformationisavailableattheendofthechapter
http://dx.doi.org/10.5772/50384
1.Introduction
Electronics have received great advance in manufacturing technology and in design
automation in the last decades. Systems-on-chip (SoC) integrating complex mixed-signal
devices with multi-million transistor circuits have been developed. This fast increase
in complexity has been reflected on the need for more engineers and tools to increase
productivity.
In the digital domain, the tools are comprehended inside a well-defined design flow that
allowsthedesignertosegmenttheprobleminvariousabstractionlevelsandthensolveitin
astraightforwardapproach.Thereareindustrystandardsfordigitaltoolsinthisdomainand
newtoolscanbeproposedtosolvespecificproblemsandbeallocatedproperlyintheflow.
Inanalogdomain, despiteofthe effortsinthe developmentofdesigntoolsbythe scientific
community,thereisstillnowell-definedflowduetothegreatcomplexityandtheinterrelation
between the several phases of design. Therefore, there is a gap in the automation level of
flows between digital and analog domain. A greaterautomation of the analog flow would
allowsmallertime-to-marketforanalogdesignandalsoformixed-signaldesigns,asanalog
sectionsareusuallythebottleneckintimerequiredtodesign.
AnalogcircuitshaveanimportantroleinmostofmodernICs. Theyareusedintheinterface
between realworld signals (which are analog) and the digitalworld, covering applications
fromanalog-to-digitalanddigital-to-analogconverterstofiltersandradiofrequencycircuits.
Therefore,productivityintheanalogdomainreflectsontheICindustryasawhole.
Thedifficultiesofautomatinganalogdesignsresultfromthelackofclearseparationofstages
intheanalogflow. Altoughtitispossibletodescribetheflowusingsomeabstractsteps,in
practicetheflowisstronglyconnectedthroughfeedbackandlow-leveldesigntasksneedtobe
consideredevenwhenthedesignisatahigh-levelstage.Therefore,acompleteanalogdesign
is usually not a straightforward process, requiring comprehension of the whole process in
ordertoperformasingletask.
©2012WeberandVanNoije,licenseeInTech.Thisisanopenaccesschapterdistributedundertheterms
oftheCreativeCommonsAttributionLicense(http://creativecommons.org/licenses/by/3.0),which
permitsunrestricteduse,distribution,andreproductioninanymedium,providedtheoriginalworkis
properlycited.
220 2Simulated Annealing – Advances, Applications and Hybridizations Will-be-set-by-IN-TECH
Otherissuethatmakestheautomationintheanalogdomainmorecomplexthaninthedigital
isthegreatnumberofdegreesoffreedominthedesignvariables,aswellasthelackofclear
interrelationamongthem. Also,analogvariablesarewithinaninfiniterangeofvaluesand
themeasurementsperformedneedtotakeintoaccountsecondandthird-ordereffects. This
means that the trade-offs that exist are not always evident and therefore very experienced
designersareneededtohavethecorrectinsightsduringthesizingofanalogblocks.
Furthermore,oncethedesignisaccomplishedforaselectedtechnology,neweffortandtime
isrequiredtodesignitforanewtechnology.
As changing technology usually means that the projecthas to start from scratch, an expert
analog designer (or a team of designers) is required once again as a change of technology
usually results in redesign from scratch. Despite all difficulties, analog design is typically
accomplished by engineers with no more than a mathematical software, an electrical
simulator, intuition and energyto perform severaltrials and errors, as no hand calculation
deliverspreciseresultsinoneattempt.
The use of CAD tools is a way to aid the designer to bridge the productivity gap between
the analog and digital domains. Synthesis is optimization procedure which does not rely
on an initial good solution. It has the objective of achieving the specifications without the
requirementofaninitialsolutionclosetotheglobalminimumprovidedbythedesigner.
Initial studies in circuit level synthesis were done in the 1980’s and were mostly
knowledge-based approaches [5], [10]. These approaches tried to capture the design
knowledgerequiredtoperformsomecircuitimplementationandimplementitinalgorithms.
Optimization-basedapproachesstartedtobemadeinthelate1980’sandarestillanactivearea
ofresearch[6],[29],[27]. Theseapproachesprovidetoolswithgreaterflexibilityandsmaller
overheadincomparisonwithknowledge-basedapproaches.
Optimization-basedapproachesarefurtherclassifiedbythewaytheyevaluateanewsolution.
Simulation-basedevaluationratherthanequation-basedevaluationwasprogressivelybeing
adoptedinordertoreducethepreparatoryeffortandtoprovidehigheraccuracy.Thistypeof
evaluationisbenefitedfromtheadvancesincomputerpowerwhichallowfastersimulations
andthereforecanreturnprecisesynthesisresultswithinatolerableamountoftime.
This chapter will introduce the basics involved in using Simulated Annealing/Simulated
Quenching as the optimization core to synthesize analog integrated circuits, as well as the
use of this algorithm together with population-based algorithms in order to improve the
effectiveness of the results. The use of multi-objective information to combine Simulated
Quenching with Genetic Algorithms as well as the use of Simulated Quenching followed
by Particle Swarm Optimization is performedto show the advantages of these techniques.
Population-based algorithms are better in dealing with multi-objective problems as they
canusepareto-dominancetocomparesolutions. CombiningSA/SQwithpopulation-based
algorithmsallowtheuseofSA/SQqualitieswiththepossibilityofovercomingissuesrelated
to the use of aggregate objective functions (used to convert multi-objectives into one) .
Multi-objective information can guide the algorithm when it is locked in a local minimum
andalsousedcombinedwithSAtoexplorethepareto-front. Inthiswork,allsynthesiswere
performedusingthesoftwareMATLABforprocessingandHSPICEforelectricalsimulations.
Thechapterisdividedasfollows. Insection2,thedefinitionoftheanalogdesignproblemis
presented. Section3presentsabriefhistoryoftheanalogsynthesisapproacheswhichused
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SimulatedAnnealing. Insection4,thealgorithmsforSA/SQandthecombinationswithGA
andPSOareshown. Section5presentssynthesisoftwoamplifiersandofavoltagereference
usingthedevelopedalgorithms.Finally,section6presentstheconclusions.
2.Analogdesignoverview
Analogdesignisacomplextaskwhichinvolvesknowledgeatdifferentlevelsofabstraction
andtheuseofoneormoreappropriatetoolsforeachlevel. Atthesystemlevel,thedesigner
mustselectthearchitecturethatbestfitstheanalogsystemthatwillbedeveloped.Thislevel
describesthelowerlevelssimplyasfunctionalblocks,whichhavenotyetdirectconnection
with the electrical devices that will implement them. The circuit level is responsible for
converting these functional blocks in electronic devices. Each high level block will have a
circuitlevel. Thetopologyand sizeofthe devicesinthislevelwilldefinethespecifications
which can be used on the system level. The layout level is responsible for converting the
dimensionvaluesfromthe circuitlevelto the maskdesignswhich willlater be usedinthe
fabricationprocess.Figure1illustratestheabstractionlevelsinvolvedinanalogdesign.
Figure1.DifferentLevels(abstractions)ofAnalogCircuitDesign.
The focus of this chapter will be restrained to analog design at circuit level, which is the
problem of finding the best device dimensions (transistors, resistors, capacitors,...) and
electricalvariables(voltagesandcurrents)inordertoachievetherequirementsforeachblock.
Inthisperspective,theparametersusedinthesystemlevelforeachblockarethespecifications
in the circuit level. The performance metrics of the circuit must be attended through the
manipulationofthedimensionvariablesofthedevices.
This is a very challenging problem as it has multi-objectives, has several local minimums
and thetimerequiredtoevaluate eachsolutionisoftennotnegligibleifasimulation-based
approachisused. Theobjectivesofananalogsynthesisandtheperformanceconstraintsare
222 4Simulated Annealing – Advances, Applications and Hybridizations Will-be-set-by-IN-TECH
usuallynon-linearfunctionsofcircuitparameters.In[2]ispresentedalistofdesirablefeatures
in an analog synthesis tool. This list includes small preparatory overhead, small synthesis
time, starting point independence, accuracy, variation-tolerance, generality and fabrication
processindependence.
The preparatory overhead is the time spent before the optimization starts in which the
designer converts the problem to the format understandable by the optimization tool. In
equation-basedevaluations,thisoverheadisusuallyhigh(weekstomonths)anddemandsan
experiencedengineertobeperformedproperly.Insimulation-basedevaluationstheoverhead
isreducedasthesimulatorwillbetheresponsibleforextractingthemeasurementsfromthe
proposed solutions. The designer usually only have to provide the circuits in a spice-like
format.
Onceallsetupisready,synthesistimeismuchfasterinequation-basedapproaches.However,
withtherapidincreaseincomputerpowerthetimerequiredforsimulation-basedapproaches
isalsobeingstronglyreduced.
Starting point independence refers to being able to achieve good solutions without the
requirement of an initial good solution provided by the designer. This is a fundamental
requirement for characterizing a procedure as synthesis and justifies the use of global
search techniques instead of using less complex local search techniques without capability
ofavoidinglocalminimums.
Accuracy is often a problem only on equation-based evaluation techniques, as the design
model needs to capture all important effects on the devices and still provides equations
manageablebytheoptimizer.Simulation-basedapproachesusetransistormodelslikeBSIM3
andBSIM4whichofferagoodtrade-offbetweenaccuracyandevaluationtime.
Variation-toleranceisthecapabilitytoprovidesolutionsthatarenotonlygoodinthenominal
device operation, but also considering the variations that might occur during fabrication
process.Generalityreferstobeingabletosynthesizeawiderangeofcircuittypes.Thisisalso
acharacteristicatwhichsimulation-basedapproachesperformbetterastheonlyrequirement
forthisapproachisthesimulatorcapabilityofprocessingthattypeofcircuit.
Fabrication process independence is the possibility of changing the fabrication technology
aftertheproblemisformulated. Thisisaveryimportantrequirementasisnotunlikelyfora
designcentertochangethefabricationprocessbeingused. Then,redesignofitsintellectual
property(IP)blocksbecomenecessary.
As it can be seenby the desiredcharacteristics, a synthesis tool for analog designneeds to
addressmostoralloftheminordertobecomeusefultotheindustry.Atoolthatrequirestoo
muchtimeandefforttobeproperlyusedoronethatdoesnotreturnsrobustsolutionswill
notfitthedesigners’expectations.
Infigure2thecircuitlevelanalogsynthesizercanbeseenasablack-boxwithitsinputsand
outputs. The designerprovidesthe topologyto be synthesized(e.g.,foldedcascode, miller
amplifier,...), the foundry technology, the specifications (e.g., gain, area, power supply,...),
the testbenches which will beusedto make the measurementsofthe circuitand finally the
synthesisconfigurations. Thesynthesizerinteractsseveraltimeswiththeelectricalsimulator
inordertoevaluatethesolutionsthatareproposedduringtheoptimizationprocedure. The
outputsareadimensionedandbiasedcircuit,thespecificationsachievedbythissolutionand
graphicsshowinganapproximationofitsparetofront.
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Figure2.InputsandOutputsoftheCircuitLevelSynthesisTool.
3.Problemdefinition
Beforewedealwiththeoptimizationofanalogcircuitdesigns,itisimportanttospendsome
effortin correctlydefining the problem. An oversimplifieddefinition, consideringonly the
most superficial measurements would either take the solver to a non-practical, non-robust
solution or lack enough hints during optimization to direct the solution to the designer
specifications.
Analog design at circuit level typically have geometric variables and electrical variables.
Geometricvariablesarethedimensionsofthedevicespresentinsideagivenblock,suchasthe
widthandlengthofthetransistor.Theyareimportanttodeterminethedevicecharacteristics
suchasthevalueofaresistor,thevalueofacapacitor,I/Vcurveofatransistorandothers.
Theinfluenceofthesegeometricvariablesonthecircuitmeasurementsisusuallynon-linear.
The effect of the geometric variables in a transistor current, which will affect the
measurements,willdependnotonlyinitsdimensionsbutalsoonthevoltagesinitsterminals.
TheequationsofaMOStransistorcanbeseeninequation(1)forlong-channelapproximation
(Schichman-Hodgesmodel):
⎧
⎪⎪⎪⎪⎪⎪⎪⎪⎨0, ifincut-offregion
W V2
ID =⎪⎪⎪⎪⎪⎪⎪⎪⎩μμnnCCOOXXWL [((VVGS--VVTH))(V1D+S-λV2DS]),, iiffiinnlsinateuarrarteiogniornegion (1)
2L GS TH DS
where ID is the drain current, W is the width of the transistor channel, L is the length, μn
istheelectronmobility,C isthegateoxidecapacitance, V isthegatetosourcevoltage,
OX GS
V isthethresholdvoltage,V isthe draintosourcevoltageand λisthe channel length
TH DS
modulationeffectparameter. Fromthesevariables,WandLaretheoneswhichthedesigner
can manipulate while COX, μn and VTH are technology dependent, and the voltages are
224 6Simulated Annealing – Advances, Applications and Hybridizations Will-be-set-by-IN-TECH
consequenceofthewholecircuitequations(thedesignerwillhaveindirectcontroluponthese
valuesbysettingthecorrectcurrentsinalltransistors).
Electrical variables used by the synthesizer are voltages or currents that are usually in the
interfaceoftheblockwithitsexternalenvironment,suchasbiascurrentsorvoltages.
Thechoiceofthevariablesisnotarbitrary. Astheywillresultinphysicaldevices,thereare
constraints that need to be addressed in order the design to be feasible. These limitations
are called design constraints [22]. They can be of two types: behavior (or functional) and
geometric (or side) constraints. Behavior constraints are usually provided by the designer
to define limitations that guarantee that the circuit will work properly, such as transistor
operationregionsorrelationsbetweendifferentdimensionsacrosstransistors.
The operation regionof a transistor is the result of the voltages between its terminals as it
canbeseenineq. (2),(3)and(4). Togetatransistorinaspecificoperationregionisoftena
problemconstraintasthiswillaffecttheoperationandrobustnessofthecircuit.
cut-off V <V (2)
GS TH
triode V <V -V and V >V (3)
DS GS TH GS TH
saturation V ≥V -V and V >V (4)
DS GS TH GS TH
Geometric constraints are usually provided by the foundry which will fabricate the chip
and referto limitations which narrow the possible widths and lengths. The most common
geometricconstraintinanalogdesignistheminimalchannellengthofthetransistors.
3.1.Multi-objectiveproblem
Therearemultipleobjectives toaddressinanalog synthesis. Eachtypeofanalog blockhas
itstypeofspecificationandusuallyagreatnumberofthemarecompetitive. Thismeansthat
usuallyimprovingonecharacteristicofthecircuitdecreasesoneormultipleothers,resulting
inthesocalleddesigntrade-offs.In[23],anexampleofthetrade-offsinvolvedinthedesignof
analogamplifiersisshown,suchaspower,gain,outputswing,linearityandothers.
On the other hand, optimization methods usually make use of only one cost function to
measure the quality of a solution. However, onmulti-objective problemsone costfunction
foreachobjectiveisrequired.Thesecostfunctionscanbelaterintegratedintoonethroughan
AggregateObjectiveFunction(AOF)oroptimizedbyamethodthatcanacceptmultiplecost
functions.Thistypeofproblemcanbedescribedby:
MinF((cid:2)x)={f ((cid:2)x),f ((cid:2)x),...,f ((cid:2)x)} (5)
1 2 k
Subjectto:
g((cid:2)x)≤0 i=1,2,...,m (6)
i
h ((cid:2)x)=0 j=1,2,...,p (7)
j
where(cid:2)x = [x1,x2,....,xn]T isavectorcontaining the decisionvariables, fi : (cid:4)n −→ (cid:4), i =
1,...,k are all the objective functions, and g,h : (cid:4)n −→ (cid:4), i = 1,...,m, j = 1,...,p are the
i j
constraintfunctionsoftheproblem.
Astherearemanyobjectives,itismorecomplicatedtocomparedifferentsolutionsthanitis
insingle-objectiveproblems.Ifonesolutionisbetterthantheotherinoneobjectivebutworse
Design of Analog Integrated Circuits Using
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Figure3.Exampleofaparetofrontfora2-dimensionaldesignspace.
inanother, onecan’tchoosewhichoneisthebetter. However,therearecasesinwhichone
solutionoutperformsanother inallspecifications, whichmeansonesolutiondominatesthe
other.
The pareto set is the set of all non-dominated solutions. They represent all the trade-offs
involvedinthesynthesis.Somedefinitionsareusedin[24]toformalizetheconceptofpareto
front:
Definition1:Giventwovectors(cid:2)x,(cid:2)y∈(cid:4)kwesaythat(cid:2)x≤(cid:2)yifx ≤y fori =1,...,k,andthat
i i
(cid:2)xdominates(cid:2)yif(cid:2)x≤(cid:2)yand(cid:2)x(cid:7)=(cid:2)y.
Definition2: Wesaythatavectorofdecisionvariables(cid:2)x ∈ χ ⊂ (cid:4)n isnon-dominatedwith
respecttoχ,ifthereisnotanother(cid:2)x(cid:9) ∈χsuchthat(cid:2)f((cid:2)x(cid:9))thatdominates(cid:2)f((cid:2)x).
Definition3:Wesaythatavectorofdecisionvariables(cid:2)x∗ ∈(cid:2)⊂(cid:4)n((cid:2)isthefeasibleregion)
isthePareto-optimalifitisnon-dominatedwithrespectto(cid:2).
∗
Definition4:TheParetoSetP isdefinedby:
P∗ ={(cid:2)x∈(cid:2)|(cid:2)xisPareto−optimal}
∗
Definition5:TheParetoFrontPF isdefinedby:
PF∗ ={(cid:2)f((cid:2)x)∈(cid:4)k|(cid:2)x∈P∗}
An illustrationof a pareto front for a two-dimensional problem can be seen in figure 3. In
this figure, both objectives are of minimization, which means a point close to (0,0) would
be preferable if it was possible. The anchor points are the extreme optimal results of the
specifications,whiletheotherpointsintheparetofrontareusuallytrade-offsbetweenseveral
specifications.
3.2.Continuousdesignspace
Simulated Annealing was initially proposed to solve combinatorial problems which use
discretevariables. Therefore,thegenerationofanewsolutionwasaccomplishedbysimply
selectingonevariabletomodifyandincreasingordecreasingonestepinthediscretespace.
226 8Simulated Annealing – Advances, Applications and Hybridizations Will-be-set-by-IN-TECH
However,transistor,resistorandcapacitordimensionsareusuallybettertreatedascontinuous
variables,astheycanassumealargerangeofvalues.Inproblemswithcontinuousvariables,
the minimum variation ΔX of a variable X becomes subjective and at the same time
fundamentaltotheprecisionandspeedoftheannealingprocess.Choosingatoomuchsmall
ΔXwillresultinanexcessivenumberofiterationsuntilthealgorithmfindsaminimum. On
theotherhand,atoomuchgreatvaluewilldecreasetheprecisioninwhichthedesignspace
isexploredandthereforeitwillbedifficulttograduallyfindthebestsolution.
Anotherissueisthatdifferenttypesofvariablesmayneeddifferentvariations.Theminimum
change in resistor’sresistance ΔR which will bestsatisfythe speedand precisioncriteriais
different than the minimum change in transistor’s channel length ΔW. The same type of
variableindifferenttypesoftechnologiesmayalsorequirethesamedistinction.Forexample,
theΔLinthechannellengthofatransistorin0.18μmtransistorwhichwillbebetterforfinding
resultsisdifferentfromtheΔLthatwillachievethesameresultsfora0.5μmtransistor.
Other differentiation that needs to be made is based on the optimization phase. The
optimization may be divided in an exploration phase and a refinement phase (which may
be mixed). If a variable is far from its optimal final value, the exploration phase is more
appropriatetotestnewvalues. Whenthevariablehasitsvalueneartheoptimalfinalvalue,
the refinement phase is better to approach the optimal solution. Modifications magnitude
shouldbegreaterintheexplorationphasethanintherefinementphase.
Therefore,itbecomescleartheneedtochange thevariablevaluesinanadaptiveapproach.
TheapproachusedforthesimulationsinthischapterisdescribedintheSimulatedAnnealing
section.
3.3.Generationofcostfunctions
The construction ofacostfunctionforeach specificationisveryimportantasitisaway to
analyzehowclosetheoptimizationisfromtheobjectiveandalsotocomparewhichobjectives
shouldbeprioritizedineachstageoftheoptimization.
When approaching the problemthrough a single-objective optimizer, the several objectives
areaggregatedinonlyoneusingaweightedsumofeachcostfunctionasineq.(8).
n
C= ∑c ·w (8)
i i
i=1
whereCisthetotalcost,iistheobjectiveindex,c isasingle-objectivecostandw istheweight
i i
ofthesingle-objectivecost.
Theoptimizerwillsensethevariationsonthetotalcostanddecideifasolutionmustbekept
or discarded. Therefore, the cost functions that compose this AOF must be designed in a
waytohaveagreaterΔc forresultsthatarefarfromthespecificationsandthereforemustbe
i
optimizedearlier.Thisgreatergradientformeasurementsdistantfromtheobjective(e.g.less
than70%ofthespecificationinanobjectivemaximization)helpstheoptimizertodevelopthe
circuitasawhole.
Althoughseveraltypesoffunctionscanbeusedtocreatethecostfunction,piecewiselinear
functionswereusedinthisworkinordertopreciselycontroltheregionsinwhichagreater
Δc/Δm shouldbeapplied,wherem isthemeasurement.Theobjectiveofeachspecification
i i i
inanalogdesigncanbeminimization,maximizationorapproximation:
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Figure4.Costfunctionforaspecificationwithobjectivemaximization.
Figure5.Costfunctionforaspecificationwithobjectiveminimization.
• Maximization: solution measurements must be equal or greater than the specification
value. ExamplesareDCGain,Cut-offfrequencyandSlewrate. Figure4showshowthis
workimplementsthistypeoffunction.
• Minimization: solutionmeasurementsmustbeequalorlessthanthespecificationvalue.
Examples are area, power consumption and noise. Figure 5 shows how this work
implementsthistypeoffunction.
• Approximation:solutionmustapproachthespecificationvalue. Examplesarethecentral
frequencyofanvoltagecontrolledoscillatorandthevoltageoutputofanvoltagereference
block.Figure6showshowthisworkimplementsthistypeoffunction.
Anindicatorcontainingthenumberofmeasuresthatresultedinfailureisusedtoassignahigh
costtothesefunctions inordertoprovideagradientevenwhendealingwithnon-working
designs. Also, the designercan choosetoputsomeorall transistorsinaspecificoperation
region. These and other constraints are added to the AOF in orderto convert the problem
fromconstrainedtounconstrained.
228 1S0imulated Annealing – Advances, Applications and Hybridizations Will-be-set-by-IN-TECH
Figure6.Costfunctionforaspecificationwithanobjectiveapproximation.
Conversionoffunctionalconstraintsintopenaltiesisperformedbyaddingnewtermstothe
AggregateObjectiveFunction.Equation(9)showsthisconversion:
n m
C= ∑c ·w +∑ p ·w (9)
i i j j
i=1 j=1
wherejisthepenaltyindex,p isthepenaltyforeachoftheconstraintsandw istheweight
j j
ofeachpenaltyandmisthenumberofpenalties. Thereisthechoiceofmakingthepenalties
morethansimpleguidelinesbydefiningw >>w forallobjectivesandpenalties.
i j
Other operationthat helps Simulated Annealing to deal with analog designproblem is the
additionofaboundarychecktoavoidfaultysimulations. Theboundarycheckisperformed
every-timeanewsolutionisproposedtoavoidvaluesoutofthegeometricconstraints.These
solutions usuallyresultin simulationerrorsand take longerthan typical ones. As they are
irrelevant, the optimizercan skipthese values and returnto the state beforethe generation
of the solution. The algorithm is kept in loop until a new solution is proposed within the
boundaries and at each attempt to generate a wrong solution the sigma of the changed
variableisreduced.
4.Simulatedannealingapproachesinanalogdesign
SimulatedAnnealingwasusedinanalogdesignsincetheearlymomentsofanalogsynthesis
wasbasedonoptimizationapproaches. Stillnow,itisoneofthemostpopularalgorithmsto
analogdesignhowevercombinedwithothertechniques.
In [9], a method for optimizing analog circuits using simulated annealing with symbolic
simulation of the solutions is proposed. The optimization was accomplished through the
useofaprogramcalledOPTIMANandusedasinputdesignequationsautomaticallyderived
using a tool called ISAAC [8]. This tool models the circuit in a set of analytic expressions
whichcanbeusedbytheoptimizationalgorithmtofastevaluateeachsolution. Later,these
toolswereintegratedintoasynthesisenvironmentcalledAMGIE[6]thatcoversthecomplete
analogdesignflow,fromspecificationtolayoutgeneration.