Design for High Performance, Low Power, and Reliable 3D Integrated Circuits PDF
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Design for High Performance, Low Power, and Reliable 3D Integrated Circuits Sung Kyu Lim Design for High Performance, Low Power, and Reliable 3D Integrated Circuits 123 SungKyuLim SchoolofElectricaland ComputerEngineering GeorgiaInstituteofTechnology 777AtlanticDriveNW Atlanta,Georgia,USA ISBN978-1-4419-9541-4 ISBN978-1-4419-9542-1(eBook) DOI10.1007/978-1-4419-9542-1 SpringerNewYorkHeidelbergDordrechtLondon LibraryofCongressControlNumber:2012949555 ©SpringerScience+BusinessMediaNewYork2013 Thisworkissubjecttocopyright.AllrightsarereservedbythePublisher,whetherthewholeorpartof thematerialisconcerned,specificallytherightsoftranslation,reprinting,reuseofillustrations,recitation, broadcasting,reproductiononmicrofilmsorinanyotherphysicalway,andtransmissionorinformation storageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilarmethodology nowknownorhereafterdeveloped.Exemptedfromthislegalreservationarebriefexcerptsinconnection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. 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Printedonacid-freepaper SpringerispartofSpringerScience+BusinessMedia(www.springer.com) To Mina,Yuna,and Jeanie Preface Istartedworkingon3DICandthrough-silicon-via(TSV)in2001whenIfirstjoined GeorgiaTech.Asayoungfacultyandaresearcher,mymissionwastofindatopic that I can devote myself onto for many yearsto come and promiseshigh risk and highreturn.Diestackingwasnotanewideain2001.But,thesimpleideaofstacking individualdies and connectingthem using vias that verticallypenetratethe whole die–thetermTSVdidnotexistorwidelyacceptedbackthen–madealotofsense tome.Thebenefitswereveryobvious:shorterinterconnects,shorterinterconnects, andshorterinterconnects(andthensmallerfootprint). As many of the readers of this book are very well aware, interconnects are a huge headache in modern (and future, too) VLSI circuits and systems. Many researchers worldwide have been struggling everyday with interconnect-related issues. So, the moment you hear that interconnect lengths will reduce naturally and significantly, you begin to smile at its related benefits: higher performance, lowerpowerconsumption,fewermetallayersused,etc.Andyes,extremememory bandwidthforthearchitects.No,IdidnotforgetaboutthecostsavingforSystem- On-Chip (SOC) developersbecause they do not have to integrate all those mixed signalcomponentsintothesamedie! Well,thingshavenotexactlybeenthewayeveryoneexpected.Despitethehuge volumeofworkandsuccessstoriesonmaterialsandmanufacturingresearchandde- velopment,effortsinarchitecture,design,andCADtoolshavebeenlaggingbehind. People have encountered electro-thermo-mechanical reliability issues associated withTSVs, andtestingbecamehighlychallengingandexpensive.Mostofall, the killerapplicationthatwilljustifythehugeinitialinvestmentonthemanufacturing lines has not been identified until recently.1 In the meantime, some have turned theirattentionto“2.5Dintegration,”whereTSVsarenotusedinthediesbutinan interposer(siliconorglass)tointegratecomponentsmountedonit. 1Manyagreethatwide-I/O3DDRAMformobileapplicationswillbethefirstmainstreamproduct thatcommercializesTSVs. vii viii Preface This book came out of the effort during the last decade (2001–2012) of 3D IC designresearch anddevelopmentat the GeorgiaTech Computer-AidedDesign (GTCAD)Laboratory,withmorefocusonthelast4years(2009–2012).Thescope of our research has expanded from physical design automation to architecture, modeling, pathfinding, and validation. We also have developed a real 3D IC that stacks one tier of 64 general-purpose cores and another tier of SRAM memory. Through this effort, we worked on the entire spectrum of design and testing for this test chip: architecture, layouts, CAD tools, package, board, and testing infrastructure.We also began to look beyondthe conventionalTSV-based 3D ICs andstartedinvestigatingmonolithic3DICdesign.The20chaptersincludedinthis book are organized to reflect this evolution. The first part of this book contains six chapters on design issues and solutions for high performance and low power 3DICs. • In Chap.1, we study the pros and cons of two distinct ways to place through- silicon-vias(TSVs)ingate-level3Dlayouts,namely,regularandirregularstyles. We also studythearea,wirelength,timing,andpoweroverheadofTSVsin3D IClayouts. • In Chap.2, we study how to build a Steiner tree for a given set of points in multipledies.WealsostudyhowtorelocateTSVsinagivensetofSteinertrees toalleviatethermalhotspotissues. • InChap.3,westudyhowtoaddbufferstoa3Dnetthatconnectsgatesinmultiple diesin3DICtooptimizesignaldelayandslew. • In Chap.4, we study how TSVs can be used to build a clock tree for 3D IC to reducethetotalpowerconsumptionwhileminimizingclockskew. • InChap.5,westudytheissuesinpowerdeliverynetworkdesignfor3DICsand theimpactofpower/groundTSVusageonpowersupplynoise. • InChap.6,westudyhowtobuildaclocktreefor3DICsothatitcanbeusedto deliverclocksignalduringpre-bondandpost-bondtesting. Thesecondpartofthisbookcontains3chaptersondesign-for-electrical-reliability for3DICs. • In Chap.7, we study the TSV-to-TSV coupling issues and investigate various waystoalleviatetheassociatedproblems. • In Chap.8, we investigate the current crowding problem at the wire-to-TSV junctioninthepowerdeliverynetworkanditsimpactonIR-drop. • In Chap.9, we study the electro-migrationfailure mechanismsin TSVs caused bythecurrentdensity,mechanicalstress,andthermalgradientissuesin3DICs. Thethirdpartofthisbookcontains3chaptersondesign-for-thermal-reliabilityfor 3DICs. • In Chap.10, we study thermal-awarearchitecturalfloorplanningfor 3D IC and itsimpactonothermetricssuchasarea,wirelength,andperformance. • In Chap.11, we study gate-level placement techniques to alleviate thermal problemsin3DICdesigns. Preface ix • In Chap.12, we investigate the issues in codesign and co-analysis of thermal, powerdelivery,andperformancetargetinga3DICthatemployeesmicro-fluidic channelsforcooling. Thefourthpartofthisbookcontains5chaptersondesign-for-mechanical-reliability for3DICs. • InChap.13,westudythefull-chipanalysisofmechanicalstressin3DICdesigns caused by the coefficient of thermal expansion (CTE) mismatch between TSV andsiliconsubstrate. • In Chap.14, we study the impact of mechanical stress on device mobility and full-chiptimingvariationsin3DIC. • InChap.15,we extendthefull-chipstudyin Chap.13toinvestigatetheimpact ofpackageelementsonthemechanicalreliabilityoftheentire3Dchip/package system. • In Chap.16, we study the impact of chip/package mechanical stress on device mobilityandfull-chippathdelayvariations. • In Chap.17, we study the impact of TSV-induced mechanical stress on crack growthbetweenTSVanditsliner(=interfacialcrack). Thelastpartofthisbookcoversothertopicson3DICdesign. • InChap.18,westudythedensity,performance,andpowerbenefitofmonolithic 3D integration, where NMOS and PMOS are placed in two different tiers and connectedwithextremelysmallmonolithicinter-tiervias(MIVs). • InChap.19,westudytheimpactofTSVscalingonthearea,wirelength,timing, andpowerqualityof3Ddesignsdoneatthecurrentandfuturetechnologynodes. • In Chap.20, we study the design, manufacturing,and testing of the 3D-MAPS (massively parallel processor with stacked memory), where one tier of 64 general-purpose cores and another tier of SRAM memory are bonded face to faceforcore-to-memorycommunicationandutilizeTSVstocommunicatewith thepackage. ThesetopicsaremostlybasedonourworkpublishedatpremierdesignandCAD conferencessuch as IEEE InternationalSolid-State Circuits Conference (ISSCC), IEEE Custom Integrated Circuits Conference (CICC), ACM Design Automation Conference (DAC), IEEE International Conference on Computer-Aided Design (ICCAD),etc.,duringlast4years(2009–2012). This book is primarily intended for circuit designers and CAD tool developers from both industry and academia who are interested in learning about what the researchersattheGeorgiaTechComputer-AidedDesign(GTCAD)Laboratoryand theircolleagueshaveexperiencedfromdesigningandvalidatinghighperformance, lowpower,andreliable3DICs.However,asignificantportionofthisbookisalso based on our collaboration with people from other areas such as manufacturing, materials, testing, software applications, and computer architecture. This book discusses the needsand outcomesof such collaborations.The materialspresented x Preface inthisbookarealsobasedonourclosecollaborationwithindustrypartnersthrough funded research projects from Intel, IBM T. J. Watson, Samsung, Qualcomm, MentorGraphics,andCadence. Despiteoureffort,thisbookmaystillcontainerrors.Wewillbetrulygratefulif youcouldhelpuscorrectthosemistakes.Pleasesendanyreportofbugs,misprints, andother erratato me at [email protected] the meantime,please visit our websiteforotherresourcesanderrata:http://users.ece.gatech.edu/limsk/3d-book. Atlanta,GA,USA SungKyuLim
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