Design Concepts for a Virtualizable Embedded MPSoC Architecture: Enabling Virtualization in Embedded Multi-Processor Systems

222 Pages·2014·8.064 MB·English

by  Alexander Biedermann (auth.)

Design Concepts for a Virtualizable
Embedded MPSoC Architecture
Alexander Biedermann
Design Concepts for a
Virtualizable Embedded
MPSoC Architecture
Enabling Virtualization in
Embedded Multi-Processor Systems
Alexander Biedermann
Darmstadt, Germany
Technische Universität Darmstadt, 2014
Darmstädter Dissertation, D17
ISBN 978-3-658-08046-4 ISBN 978-3-658-08047-1 (eBook)
DOI 10.1007/978-3-658-08047-1
Library of Congress Control Number: 2014954234
Springer Vieweg
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Abstract
Inthepresentwork,agenerichardware-basedvirtualizationarchitectureisintroduced.
The proposed virtualization concept transforms an array of off-the-shelf embedded
processorsintoasystemwithhighexecutiondynamism. Atanypointintime,tasks
maybeshiftedamongtheprocessorarraytransparently. Neitherthesoftwareoftasks
northeprocessorcoreshavetobemodifiedinordertoenablethisfeature. Thework
detailstask-processorinterconnection,virtualizedtaskcommunicationaswellasmeans
forenergyawarenessandfaulttoleranceinavirtualizableMPSoC.
Based on this architecture, concepts for the design of embedded multi-processor
systems with the ability for a dynamic reshaping of their initial configuration are
highlighted. This includes energy aware systems, fault tolerant systems as well as
parallelizedsystems. Forthelatter,theso-calledAgileProcessingschemeisintroduced,
whichenablesaseamlesstransitionbetweensequentialandparallelexecutionschemes
oftasks. Thedesignofvirtualizablesystemsisfurthermoreaidedbyadedicateddesign
framework,whichintegratesintoexisting,commercialdesignflows.
Application examples taken from different domains in embedded system design
feature specific optimization goals and demonstrate the feasibility of the proposed
designconceptsandofthevirtualizationarchitecture. Forthispurpose,prototyped
virtualizablemulti-processordesignshavebeensuccessfullysynthesizedforFPGAs.
Zusammenfassung
DievorliegendeArbeitstellteingenerischeshardware-basiertesVirtualisierungskonzept
vor, das aus einem Array aus eingebetteten Standardprozessoren ein System mit
hoherAusführungsdynamikschafft.TaskskönnenzurLaufzeitzujedemZeitpunkt
transparentzwischendenProzessorenimArrayverschobenwerden.Wederexistierende
SoftwarederTasks,nochdieProzessorenbedürfenhierbeieinerspeziellenAnpassung.
Die Arbeit detailliert die skalierbare Task-Prozessoranbindung, virtualisierte Task-
Kommunikation,sowieMaßnahmenzurEnergieverwaltungundFehlererkennungbzw.
-maskierunginvirtualisierbarenSystemen.
Auf Basis des vorgestellten Virtualisierungskonzepts können eingebettete Multi-
ProzessorsystemeunterschiedlicherAusprägungdesigntwerden.Diesbeinhaltetener-
gie-bewusste Systeme, fehlertolerante Systeme oder parallel verarbeitende Systeme.
Beiletzteremwirddassog.AgileProcessing-SchemaalsnahtloseTransitionzwischen
sequentiellerundparallelerAusführungvonTaskseingeführt.DasDesignvirtualisier-
barerSystemewirddurcheineigensbereitgestelltesDesign-Frameworkunterstützt,
daseinenahtloseAnbindunganexistierende,kommerzielleDesignFlowsbietet.
Das Entwurfskonzept wird durch Anwendungsbeispiele aus eingebetteten Syste-
menmitjeweilsunterschiedlichenOptimierungszielendemonstriert.Hierfürwurden
entsprechendeDesignsprototypischfürFPGAssynthetisiert.
Acknowledgments
Thisthesiswouldnotexistwithoutthehelp,advice,andguidancebyalotofpeople.
Firstofall,IwouldliketothankProf. SorinA.Hussforsupervisingmythesis. For
morethanhalfadecade,Prof. Hussguidedmeonthejourneytowardsthisthesisby
givingadvicewhenIwasstuck,bypointingoutlinksIhadnotseenandbysharing
experienceIwaslacking. Iamgratefulforhavinghadtheopportunitytoresearchand
workattheIntegratedandCircuitsLabwhereIcouldpursueandevolvemyideas.
Second, I would like to thank Prof. Jörg Henkel for taking the time to be second
assessorofthisthesis.
At the Integrated Circuits and Systems Lab, I especially thank Maria Tiedemann,
whoalwaysprovidedkindandexperiencedsupportinallmattersIstillconsiderbeing
mysteriousandinscrutable,suchastravelexpenseaccounting.
Ideasevolvebothinphasesofsecludedthinkingaswellasinlivelydebates. Forthe
latter,IthankmycolleaguesTomAßmuth,AttilaJaeger,FelixMadlener,GregorMolter,
andQizhiTianfordelightfulhoursofferviddiscussionsaboutLife,theUniverseand
Everything. IalsothankmyothercolleaguesattheIntegratedCircuitsandSystemsLab
andattheCenterforAdvancedSecurityResearchDarmstadt(CASED),inparticular
Tolga Arul, Carsten Büttner, Thomas Feller, Annelie Heuser, Adeel Israr, Zheng Lu,
SunilMalipatlolla,AndréSeffrin,AbdulhadiShoufan,MarcStöttinger,HagenStübing,
andMichaelZohner.
Tensofthousandslinesofimplementationworkbyalotofstudentshaveenabled
thatthisworkisnotsolelyaconstructofideas,butisbasedonworkingprototypes,
whichallowedtotestandtodemonstratetheopportunitiesarisingfromtheproposed
virtualizationconcept. Inthisconnection,IespeciallythankBorisDreyerfordiscussing
ideasandprovidingexceptionalworkoverthelastthreeyears. Ifurthermorethank
ClemensBergmann,AntonioGavinoCasu,HieuHaChi,QuocHienDang,Johannes
Decher, Binh Vu Duc, Nicolas Eicke, Steffen Fleckenstein, Sebastian Funke, Peter
Glöckner,MaikGörtz,ChristopherHuth,InacKadir,MichaelKoch,ThorstenJacobi,
Dan Le, Randolph Lieding, Wei Lin, Kevin Luck, Mischa Lundberg, Amir Naseri,
JoelNjeukam,JanPost,AndreasRjasanow,LucasRothamel,TobiasRückelt,Gregor
Rynkowski,DanielSchneider,KaiSchwierczek,OmidPahlevanSharif,JohannesSimon,
NielsStröher,MarkusTasch,DoThanhTung,ManuelWeiel,andMatthiasZöllner.
Finally,Ithankmybelovedfamilyforneverdemandingtoomuchdetailaboutmy
researchabout“somethingwithcomputers”atthecoffeetable.
AlexanderBiedermann
Contents
1 The“Nulticore”Dilemma 1
2 VirtualizableArchitectureforembeddedMPSoC 5
2.1 TheTermVirtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 VirtualizationforEmbeddedMulti-ProcessorArchitectures . . . . . . . 7
2.2.1 CharacteristicsofEmbeddedProcessors . . . . . . . . . . . . . . 7
2.2.2 PurposeofVirtualizationinEmbeddedMulti-ProcessorArrays . 9
2.2.3 RequirementsforEmbeddedVirtualization . . . . . . . . . . . . 12
2.2.4 PrerequisitestoenableVirtualizationFeatures . . . . . . . . . . . 13
2.2.5 VirtualizationProcedure. . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.6 AnalysisandCharacteristicsoftheVirtualizationProcedure. . . 23
2.2.7 IntermediateConclusions . . . . . . . . . . . . . . . . . . . . . . . 28
2.3 DynamicallyReconfigurableTask-to-ProcessorInterconnectionNetwork 30
2.3.1 InterconnectionRequirementsforavirtualizableMPSoC . . . . 30
2.3.2 ArchitecturalAlternatives . . . . . . . . . . . . . . . . . . . . . . . 32
2.3.3 PermutationNetworks. . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3.4 ASortingPermutationNetworkasTask-ProcessorInterconnect 39
2.3.5 Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.3.6 IntermediateConclusions . . . . . . . . . . . . . . . . . . . . . . . 57
2.4 TaskSchedulingviaInterconnectionNetwork . . . . . . . . . . . . . . . 59
2.4.1 BindingDefinitionsofTaskGroupsandTaskBudgets . . . . . . 59
2.4.2 Schedulingann-to-1Relation. . . . . . . . . . . . . . . . . . . . . 61
2.4.3 Schedulingseveraln-to-1Relations . . . . . . . . . . . . . . . . . 63
2.4.4 Self-SchedulingofTasks . . . . . . . . . . . . . . . . . . . . . . . . 64
2.4.5 IntermediateConclusions . . . . . . . . . . . . . . . . . . . . . . . 75
2.5 VirtualizedTask-to-TaskCommunication . . . . . . . . . . . . . . . . . . 76
2.5.1 CommunicationAlternatives . . . . . . . . . . . . . . . . . . . . . 76
2.5.2 ConventionalPoint-to-PointTransferinnon-VirtualizedSystems 79
2.5.3 ArchitecturalEnhancementsandCodeChanges . . . . . . . . . . 81
2.5.4 BasicCommunicationScheme . . . . . . . . . . . . . . . . . . . . 83
2.5.5 EnhancedCommunicationScheme . . . . . . . . . . . . . . . . . 89
2.5.6 PropertiesandAdvancedFeatures . . . . . . . . . . . . . . . . . . 93
2.6 ReliabilityFeaturesoftheVirtualizationLayer . . . . . . . . . . . . . . . 95
2.7 FeaturesforEnergyManagement. . . . . . . . . . . . . . . . . . . . . . . 101
XIV Contents
2.8 IntermediateConclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3 TheVirtualizableMPSoC:Requirements,Concepts,andDesignFlows 107
3.1 RequirementsforDesigningonTopofthevirtualizableArchitecture . . 109
3.1.1 WeaknessesofExistingDesignTools . . . . . . . . . . . . . . . . 109
3.1.2 TheFripGaDesignFramework . . . . . . . . . . . . . . . . . . . . 110
3.2 DesignConceptsforReliable,Self-HealingSystems . . . . . . . . . . . . 116
3.2.1 DynamicBindingStrategies. . . . . . . . . . . . . . . . . . . . . . 117
3.2.2 Self-HealingStrategiesinthevirtualizableMPSoC . . . . . . . . 119
3.3 DesignFlowforParallelizedExecution . . . . . . . . . . . . . . . . . . . 122
3.3.1 ProblemMotivation . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.3.2 ParallelizationTopologies . . . . . . . . . . . . . . . . . . . . . . . 123
3.3.3 DataDependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
3.3.4 DesignFlow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.3.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
3.4 DesignFlowforAgileProcessing. . . . . . . . . . . . . . . . . . . . . . . 135
3.4.1 MotivationandChallenge . . . . . . . . . . . . . . . . . . . . . . . 135
3.4.2 Prerequisites. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
3.4.3 DesignFlowModification . . . . . . . . . . . . . . . . . . . . . . . 136
3.4.4 SchedulingSchemesforAgileProcessingDesigns. . . . . . . . . 141
3.4.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
4 ApplicationScenarios 149
4.1 ReshapinginanAutomotiveAssistanceSystem . . . . . . . . . . . . . . 149
4.1.1 SystemArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . 150
4.1.2 DriverAssistanceTasks . . . . . . . . . . . . . . . . . . . . . . . . 150
4.1.3 RoadTypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.1.4 FunctionalProfiles . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
4.1.5 TimingConstraints . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
4.1.6 BindingDerivation . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
4.1.7 TaskScheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
4.1.8 SetupoftheMPSoCandBindingStorage. . . . . . . . . . . . . . 158
4.1.9 FunctionalReshaping . . . . . . . . . . . . . . . . . . . . . . . . . 160
4.1.10 ReliabilityReshaping . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.1.11 SynthesisEvaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.1.12 OutcomeandOutlook . . . . . . . . . . . . . . . . . . . . . . . . . 170
4.2 ReshapinginanEnergy-ConstrainedQuadrocopterSystem . . . . . . . 172
4.2.1 EnvisagedScenario. . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.2.2 SensorsandControlSystemsoftheQuadrocopter . . . . . . . . 174
4.2.3 ExampleMissionSequence . . . . . . . . . . . . . . . . . . . . . . 176
4.2.4 RoleofthevirtualizableMPSoC . . . . . . . . . . . . . . . . . . . 178