Delft University of Technology Reducing Switching Artifacts in Chopper Amplifiers

209 Pages·2017·5.95 MB·English

Delft University of Technology

Reducing Switching Artifacts in Chopper Amplifiers
Kusuda, Yoshinori
DOI
10.4233/uuid:62585ae8-da35-459e-bf90-f53f7d0de32c
Publication date
2018
Document Version
Final published version
Citation (APA)
Kusuda, Y. (2018). Reducing Switching Artifacts in Chopper Amplifiers.
https://doi.org/10.4233/uuid:62585ae8-da35-459e-bf90-f53f7d0de32c
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Reducing Switching Artifacts
in Chopper Amplifiers

Yoshinori Kusuda

Reducing Switching Artifacts
in Chopper Amplifiers

Proefschrift

ter verkrijging van de graad van doctor
aan de Technische Universiteit Delft,
op gezag van de Rector Magnificus prof. dr.ir. T.H.J.J. van der Hagen;
voorzitter van het College voor Promoties,
in het openbaar te verdedigen op
maandag 30 april 2018 om 15:00 uur

door

Yoshinori KUSUDA
Elektrotechnisch ingenieur,
Master of Science van Tokyo Instituut van Technologie, Japan
geboren te Kobe, Japan
Dit proefschrift is goedgekeurd door de promotor:
Prof. dr. ir. K.A.A. Makinwa

Samenstelling promotiecommissie:

Rector Magnicus, voorzitter
Prof. dr. ir. K.A.A. Makinwa, Technische Universiteit Delft, promotor

Onafhankelijke leden:
Dr. Q. Fan Technische Universiteit Delft
Prof. dr. ir. E. Cantatore Technische Universiteit Eindhoven
Prof. dr. W.M.C. Sansen em.hgl Katholieke Universiteit Leuven
Prof. dr. ir. A.J.P. Theuwissen Technische Universiteit Delft
Prof. dr. ir. W.A. Serdijn Technische Universiteit Delft
Prof. dr. ir. J.H. Huijsing em.hgl Technische Universiteit Delft

Printed by Ipskamp Printing, Enschede, the Netherlands
ISBN: 978-94-028-0997-8
Copyright © 2018 by Yoshinori Kusuda
All rights reserved. No part of this publication may be reproduced or distributed in any form of by any means, or
stored in a database or retrieval system, without any prior permission of the copyright owner.
To my wife Kyoko and children Ryoko, Yukinori, and Kazunori

Contents
Chapter 1 Introduction.......................................................................................................... 1 
1.1  Precision Data Acquisition Signal Chain ......................................................................... 2 
1.2  CMOS Operational Amplifiers ........................................................................................ 3 
1.2.1  Functionality ............................................................................................................. 3 
1.2.2  Offset and Noise ....................................................................................................... 5 
1.2.3  Summary ................................................................................................................... 6 
1.3  Chopping Principle ........................................................................................................... 7 
1.4  Traditional Applications of Chopper Op-Amps ............................................................... 8 
1.4.1  Sensor Signal Conditioning ...................................................................................... 8 
1.4.2  Current Sensing ....................................................................................................... 10 
1.4.3  Summary ................................................................................................................. 11 
1.5  Newer Applications of Chopper Op-Amps .................................................................... 12 
1.5.1  Biomedical Sensing Front-End ............................................................................... 12 
1.5.2  Reference and DAC Buffers ................................................................................... 13 
1.5.3  Process Control Data Acquisition Signal Chain ..................................................... 14 
1.6  Challenges ...................................................................................................................... 15 
1.7  Organization of the Thesis ............................................................................................. 15 
1.8  References ...................................................................................................................... 17 
Chapter 2 Offset Cancellation Techniques ........................................................................ 21 
2.1  Offset Trimming ............................................................................................................. 22 
2.2  MOS Switches ................................................................................................................ 23 
2.2.1  Realization and On-Resistance ............................................................................... 23 
2.2.2  Charge Injection ...................................................................................................... 24 
2.2.3  Cancellation of Charge Injection ............................................................................ 25 
2.3  Auto-Zeroing .................................................................................................................. 27 
2.3.1  Principle .................................................................................................................. 27 
2.3.2  Residual Offset........................................................................................................ 27 
2.3.3  Broadband Noise Folding ....................................................................................... 28 
2.3.4  Ping-Pong Auto-Zeroing ......................................................................................... 30 
2.4  Chopping ........................................................................................................................ 31
2.4.1  Up-Modulated Ripple ............................................................................................. 31 
2.4.2  Glitches ................................................................................................................... 33 
2.4.3  Input Bias Current and Residual Offset .................................................................. 34 
2.4.4  Dynamic Switching Conductance ........................................................................... 38 
2.4.5  Summary of the Errors ............................................................................................ 39 
2.5  Comparison of the Techniques ....................................................................................... 42 
2.6  References ...................................................................................................................... 43 
Chapter 3 Methods of Reducing Chopper Switching Artifacts ....................................... 47 
3.1  Residual Offset Reduction Techniques .......................................................................... 48 
3.1.1  Filtering the Glitches ............................................................................................... 48 
3.1.2  Dead-Timed Down-Modulation .............................................................................. 50 
3.1.3  Nested Chopping ..................................................................................................... 50 
3.2  Ripple Reduction Techniques ........................................................................................ 52 
3.2.1  Multi-Path Chopper Offset Stabilization ................................................................ 52 
3.2.2  Switched Capacitor Notch Filter ............................................................................. 54 
3.2.3  High-Pass Filtering ................................................................................................. 56 
3.2.4  Initial Offset Trimming ........................................................................................... 58 
3.2.5  Combination with Auto-Zeroing ............................................................................. 58 
3.2.6  AC-Coupled Ripple Reduction Loop ...................................................................... 62 
3.2.7  Digitally Assisted Ripple Reduction Loop ............................................................. 64 
3.3  Comparison of the Techniques ....................................................................................... 66 
3.4  References ...................................................................................................................... 69 
Chapter 4 Chopper Op-Amp with Auto-Correction Feedback ....................................... 71 
4.1  Motivation ...................................................................................................................... 72 
4.2  Op-Amp and Ripple Reduction Architecture ................................................................. 73 
4.2.1  Basic Three Stage Chopper Op-Amp ..................................................................... 73 
4.2.2  Auto-Correction Feedback ...................................................................................... 74 
4.2.3  Switched Capacitor Notch Filter (SC-NF) .............................................................. 75 
4.2.4  High Frequency Path (HFP) and Overall Op-Amp ................................................. 77 
4.3  Residual Error Analysis ................................................................................................. 79 
4.3.1  ACFB Loop Gain .................................................................................................... 80 
4.3.2  Residual Ripple ....................................................................................................... 82 
4.3.3  Residual Offset........................................................................................................ 82 
4.3.4  Summary ................................................................................................................. 83 
4.4  Circuit Implementation .................................................................................................. 86
4.4.1  Input and Nulling Transconductors ........................................................................ 86 
4.4.2  Second, Output, and Feedforward Transconductors ............................................... 87 
4.4.3  Clock Generator ...................................................................................................... 88 
4.4.4  Noise Analysis ........................................................................................................ 91 
4.5  Measurement Results ..................................................................................................... 92 
4.6  Conclusions .................................................................................................................... 98 
4.7  References .................................................................................................................... 100 
Chapter 5 Chopper Op-Amp with Adaptive Clock Boosting Technique ..................... 103 
5.1  Motivation .................................................................................................................... 104 
5.2  Op-Amp Architecture ................................................................................................... 105 
5.2.1  Conventional Three Stage Chopper Op-Amp and Frequency Compensation ...... 105 
5.2.2  Frequency Compensation Using a Current Attenuator and a Dummy Differential
_______Output ................................................................................................................... 107 
5.2.3  Overall Op-Amp Employing Auto-Correction Feedback ..................................... 109 
5.2.4  ACFB Loop Gain Including Active Integrator ..................................................... 110 
5.2.5  High Frequency Path (HFP) .................................................................................. 112 
5.3  Transconductor Circuits ............................................................................................... 113 
5.3.1  Input and Nulling Transconductors with the Current Attenuator ......................... 113 
5.3.2  Noise Analysis and Optimization ......................................................................... 114 
5.3.3  Residual Offset and CMRR Analysis ................................................................... 116 
5.3.4  Second and Output Transconductors .................................................................... 117 
5.4  Input Chopper ............................................................................................................... 118 
5.4.1  Conventional CMOS Switches ............................................................................. 118 
5.4.2  Input Chopper Employing Adaptive Clock Boosting Technique ......................... 119 
5.4.3  Adaptive Clock Booster Circuit ............................................................................ 121 
5.4.4  Common-Mode Buffer.......................................................................................... 123 
5.5  Measurement Results ................................................................................................... 124 
5.6  Conclusion .................................................................................................................... 130 
5.7  References .................................................................................................................... 132 
Chapter 6 Auto-Zero and Chopper Op-Amp with Clock Interleaving and Input Bias
_____________Current Trimming Techniques .................................................................... 135 
6.1  Motivation .................................................................................................................... 136 
6.2  Input Transconductor Architecture .............................................................................. 137 
6.2.1  Previous High Voltage Input Transconductors ..................................................... 138 
6.2.2  Capacitively-Coupled Auto-Zero and Chopper Input Transconductor ................ 139