dec :: dsa :: mscp :: MSCP Patent 4449182

47 Pages·2.5 MB·English

United States Patent
1191 [11] 4,449,182
Rubinson et al. [45] May 15, 1984
[54) INTERFACE BETWEEN A PAIR OF 4,318,174 3/1982 Suzuki et al. ....................... 364/200
PROCESSORS, SUCH AS HOST AND 4,334,305 6/1982 Girardi ................................ 364/200
PERIPHERAL-CONTROLLING
Primary Examiner-Joseph F. Ruggiero
PROCESSORS IN DATA PROCESSING
Assistant Examiner-Gary V. Harkcom
SYSTEMS
Attorney, Agent, or Firm-Cesari and McKenna
[75] Inventors: Barry L. Rubinson; Edward A.
(57] ABSTRACT
Gardner; William A. Grace; Richard
F. Lary; Dale R. Keck, all of An interface mechanism (10) between two processors,
Colorado Springs, Colo. such as a host processor (70) and a processor (31) in an
intelligent controller (30) for mass storage devices (40),
[73] Assignee: Digital F.quipment Corporation,
and utilizing a set of data structures employing a dedi
Maynard, Mass.
cated communications region (80A) in host memory
[21] Appl. No.: 308,826 (80). Interprocessor commands and responses are com
municated as packets over an 1/0 bus (60) of the host
[22] Filed: Oct. 5, 1981
(70), · to and from the communication region (80A),
(51] Int. CJ.3 ......................... G06F 9/46; G06F 15/16 through a pair of ring-type queues (800) and (SOE). The
(52] U.S. Cl ..................................................... 364/200 entry of each ring location (e.g., 132, 134, 136, 138)
[58] Field of Search ... 364/200 MS File, 900 MS File; points to another location in the communications region
371/21 where a command or response is placed. The filling and
emptying of ring entries (132-138) is controlled through
[56] References Cited
the use of an 'ownership' byte or bit (278) associated
U.S. PATENT DOCUMENTS with each entry. The ownership bit (278) is placed in a
3,940,601 2/1976 Henry et al. ................. 235/153 AC first state when the message source (70 or 31) has filled
4,145,739 3/1979 Dunning et al. .................... 364/200 the entry and in a second state when the entry has been
4,153,934 5/1979 Sato ..................................... 364/200 emptied. Each processor keeps track of the rings' status,
4, 181,937 1/1980 Hattori et al. ...................... 364/200 to prevent the sending of more messages than the rings
4,195,351 3/1980 Barner et al. ....................... 364/900 can hold. These rings permit each processor to operate
4,204,251 5/1980 Brudevold .......................... 364/200
at its own speed, without creating race conditions and
4,212,057 7/1980 Devlin et al. ....................... 364/200
obviate the need for hardware interlock capability on
4,214,305 7/1980 Tokita et al. ........................ 364/200
the I/0 bus (60).
4,237,534 12/1980 Felix .................................... 364/200
4,268,907 5/1981 Porter et al. ........................ 364/200
4,282,572 8/1981 Moore et al. ....................... 364/200 21 Claims, 19 Drawing Figures
----- -- ----- ----------1
l ----- I 32.
~ I HOST COMMAND RING PTR 1---1
-CO-MMA-ND -INTE-RRU-PT I 14-31 4 II
HOST RESPONSE RING PlR
RESPONSE INTERRUPT I
81A
I I
30 l
BOA I BUFFER - I 131
TRANSITION e
70 INDICATOR 136 -~ ~~jl
I ••
•
I
CPU TRANSITION I BUFFER 37
M
INDICATOR I
IP
I
I SA
38
SYSTEM BUS
110
BUS kDAPTER
L ___ -- - 60
1/0 BUS
c
.
.
V)
~
r----H-OS-T ---, r--CO-N-TR-O-LL-ER- -,
.......
a(t)
I I I I
I 1/0 I HIGH-LEVEL 1/0 I HIGH-LEVEL I
7 1 •
I CLASS ~, - PROTOCOL- - 1/0 PROTOCOL I
f
I DRIVER I 1A I SERVER I -
r:I _41 _1 _3~-1+1- --· ---2-Ir- --5l- ~·--h! Fig. f .-.V l
1
I I I
\0
I I PORT 1--!_ SOMMUNICATIONS_ J. • PORT 11 00
~
I SERVER I PROTOCOL 1 SERVER I
JI
I t_ ___ _: ____ J ____
~-----
I l'o
en
71 :r
-~
J ·l -n I .~....
a-1-
PORT PORT
I ' COMMUNICATIONS MECHANISM 9 -0
"°')
L___ _ ________ _J
~
40
10 2
60 50 ,.~
HOST INTER- .. -.I CONTROLLER ... DISK
COMPUTER FACE l I .,. DRIVE Fig.2 ~
~
"°
,.
' --v / 0io-06
20 t-.)
c
.•
Vl
,-----------
-
1 ----------
a~
I' - - - - - - ~aoe II HOST COMMAND RING PTR 3-2 , =(t>
~MMAND ~ERRllPT ~
I I 34 I """'"
eoc HOST RESPONSE RING PTR
RESPONSE 1NTERRilPT I 1 I a:
I
- - - 81A I
1 I -
I I ~
80A RESPONSERING - 800 ~ I I -
I 10 -------- TRANSITION I BUFIF ER 31 ~V \
- - - - - - INDICATOR j 36
'°
•
------ I • PROCESSOR 00
• ~
I
CPU COMMAND RING TRANSITION I BUFFER 37
N
INDICATOR I
IP c.n
:r
(1)
I I .(.1..).
SA
"k' I II I I N
-Si
38
SYSTEM BUS
~
90 I
I
110 I
LI I BUS ADAPTER
--- --- -- ________ __JI 60 Fig. 3A ..
~
~
I/O BUS ..~
\0
........
00
N
~
.e n
~
f""t"
O>
=:s
f""t"
~
-
~
-
Vt
~
139
\0
135 135 00
~
~B+~
(EMPTY)
Cl.>
:r
('!)
~
VJ
-
~
~
Fig. 38 Fig. 3C
~
"'
~
~
\0
"'
1--l
00
N
U.S. Patent 4,449,182
May 15, 1984 Sheet 4 of 14
CONTROLLER PORT
ENTER
I
I
NO I
I
204 I
I
WRITE RESPONSE I
TO REsPgNsE RING; I
SET & "F"
IBI I"T S I
YES
NO
210
Fig. 4A GENERATE
INTERRUPT
REQUEST
TO FIG. 48
U.S. Patent 4,449,182
May 15, 1984 Sheet 5 of 14
NO
YES 214
SERVICE
INTERRUPT & PROCESS
RESPONSE
216
UPDATE HOST'S
RING POINTER
TO FIG. 4C
Fig. 48
U.S. Patent 4,449,182
May 15, 1984 Sheet 6 of 14
220 222
IF 1ST TIME. REI NIT.
START TIMER TIME-OUT CONTROLLER
STOP
YES
224
PUT COMMAND
ADDRESS IN
C. RING ENTRY
SET FLAG
230
SET 11011
WRITE TO IP
AFTER COMMAND SENT.
UPDATE RING Fig. 5
TO FIG. 6
U.S. Patent 4,449,182
May 1s, 1984 Sheet 7 of 14
FROM FIG. 5
CONTROLLER DETECTS 234
HOST WRITE TO
IP
READ INTO BUFFER
242 SET FLAG BIT;
CHANGE OWNERSHIP
BIT
INTERRUPT
Fig. 6 INCREMENT 250
POINTER
U.S. Patent 4,449,182
May 15, 1984 Sheet 8 of 14
15 8 7 0
-4 RESERVED }~
254 ~
-3 ADP CH RSVD
256 -=2
-- GMO INT
}~
258
-1 RSP INT
252
~
RINGBAS
f- RSP DSC 0 ~
+1
800
-
I- RSP DSC tJ
RINGBASE•2 N-1
-
RINGBASE•2 N
I- CMD DSC 0
SOE
-
I- CMD DSC M
RINGBASE•2M•2 N-2
Fig. 7
U.S. Patent May 1s, 1984 Sheet 9 of 14 4,449,182
15 0
260'-.,
262
0 ~
0 F RESERVED Q Q Q Q u u
.
J 1 276T) 2J 7~ 2 J J
27 8 280 Fig. 8
274 270 266
15 8 7 4 3 IJ
282
-2 MSG LENGTH ,2so ~
,
286 288
-1 -~ CONNECTION ID MSGTYP CREDITS ~:
TEXT•0 MB1 MB0 .p
+1 MB3 MB2
MB•-1 MBn-2
J
284m
Fig. 9
0
298,
ADAPTER CHANNEL RSV Q Q Q Q u u
.
~ ~3 00'Ti941
. ~ol:{
Fig. 10
306 3(2 296