Cmos Memory Circuits

566 Pages·2002·5.3 MB·English

by  Tegze P. Haraszti (auth.)

CMOS MEMORY CIRCUITS
CMOS MEMORY CIRCUITS
by
Tegze P. Haraszti
Microcirc Associates
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON , DORDRECHT, LONDON, MOSCOW
eBook ISBN 0-306-47035-7
Print ISBN 0-792-37950-0
©2002 Kluwer Academic Publishers
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Contents
Preface ......................................................................................................... xi
Conventions..................................................................................................... xvi
Chapter 1. Introduction to CMOS Memories.........................................1
1.1 Classification and Characterization of CMOS Memories................................2
1.2 Random Access Memories.............................................................................10
1.2.1 Fundamentals......................................................................................10
1.2.2 Dynamic Random Access Memories (DRAMS).................................11
1.2.3 Pipelining in Extended Data Output (EDO) and
Burst EDO (BEDO) DRAMS.............................................................20
1.2.4 Synchronous DRAMS(SDRAMs) ....................................................25
1.2.5 Wide DRAMs.....................................................................................31
1.2.6 Video DRAMs....................................................................................33
1.2.7 Static Random Access Memories (SRAMs).......................................36
1.2.8 Pseudo SRAMs...................................................................................40
1.2.9 Read Only Memories (ROMs)............................................................41
1.3 Sequential Access Memories (SAMs)............................................................42
1.3.1 Principles............................................................................................42
1.3.2 RAM-Based SAMs.............................................................................44
1.3.3 Shift-Register Based SAMs................................................................45
1.3.4 Shuffle Memories...............................................................................48
1.3.5 First-In-First-Out Memories (FIFOs).................................................51
1.4 Content Addressable Memories (CAMS).......................................................54
1.4.1 Basics.................................................................................................54
1.4.2 All-Parallel CAMS..............................................................................56
vi CMOS Memory Circuits
1.4.3 Word-Serial-Bit-Parallel CAMs.........................................................58
1.4.4 Word-Parallel-Bit-Serial CAMs.........................................................59
1.5 Special Memories and Combinations.............................................................61
1.5.1 Cache-Memory Fundamentals............................................................61
1.5.2 Basic Cache Organizations.................................................................65
1.5.3 DRAM-Cache Combinations .............................................................70
1.5.4 Enhanced DRAM (EDRAM).............................................................70
1.5.5 Cached DRAM (CDRAM).................................................................72
1.5.6 Rambus DRAM (RDRAM)................................................................73
1.5.7 Virtual Channel Memory (VCM).......................................................76
1.6 Nonranked and Hierarchical Memory Organizations.....................................80
Chapter 2. Memory Cells...................................................................................85
2.1 Basics, Classifications and Objectives...........................................................86
2.2 Dynamic One-Transistor-One-Capacitor Random Access Memory Cell.......89
2.2.1 Dynamic Storage and Refresh............................................................89
2.1.2 Write and Read Signals......................................................................92
2.1.3 Design Objectives and Trade-offs......................................................96
2.1.4 Implementation Issues........................................................................97
2.1.4.1 Insulator Thickness...............................................................97
2.1.4.2 Insulator Material .................................................................98
2.1.4.3 Parasitic Capacitances.........................................................103
2.1.4.4 Effective Capacitor Area....................................................105
2.3 Dynamic Three-Transistor Random Access Memory Cell...........................110
2.3.1 Description .......................................................................................110
2.3.2 Brief Analysis...................................................................................111
2.4 Static 6-Transistor Random Access Memory Cell .......................................113
2.4.1 Static Full-Complementary Storage.................................................113
2.1.2 Write and Read Analysis..................................................................116
2.1.3 Design Objectives and Concerns......................................................121
2.1.4 Implementations ...............................................................................122
2.5 Static Four-Transistor-Two-Resistor Random Access
Memory Cells...............................................................................................125
2.5.1 Static Noncomplementary Storage................................................125
2.5.2 Design and Implementation...........................................................128
2.6 Read-Only Memory Cells ...........................................................................132
2.6.1 Read-Only Storage...........................................................................132
2.6.2 Programming and Design................................................................134
2.7 Shift-Register Cells..................................................................................136
2.7.1 Data Shifting ....................................................................................136
2.7.2 Dynamic Shift-Register Cells...........................................................138
2.7.3 Static Shift-Register Cells ................................................................143
2.8 Content Addressable Memory Cells.............................................................146
2.8.1 Associative Access...........................................................................146
2.8.2 Circuit Implementations...................................................................148
2.9 Other Memory Cells.....................................................................................151
2.9.1 Considerations for Uses....................................................................151
2.9.2 Tunnel-Diode Based Memory Cells.................................................152
Contents vii
2.9.3 Charge Coupled Device..................................................................154
2.9.4 Multiport Memory Cells.................................................................156
2.9.5 Derivative Memory Cells...............................................................158
Chapter 3. Sense Amplifiers...............................................................163
3.1 Sense Circuits.............................................................................................164
3.1.1 Data Sensing...................................................................................164
3.1.2 Operation Margins..........................................................................166
3.1.3 Terms Determining Operation Margins..........................................171
3.1.3.1 Supply Voltage.................................................................171
3.1.3.2 Threshold Voltage Drop...................................................171
3.1.3.3 Leakage Currents..............................................................173
3.1.3.4 Charge-Couplings .............................................................176
3.1.3.5 Imbalances ........................................................................179
3.1.3.6 Other Specific Effects.......................................................181
3.1.3.7 Precharge Level Variations...............................................182
3.2 Sense Amplifiers in General.......................................................................184
3.2.1 Basics .............................................................................................184
3.2.2 Designing Sense Amplifiers...........................................................187
3.2.3 Classification..................................................................................190
3.3 Differential Voltage Sense Amplifiers .......................................................192
3.3.1 Basic Differential Voltage Amplifier .............................................192
3.3.1.1 Description and Operation................................................192
3.3.1.2 DC Analysis......................................................................193
3.3.1.3 AC Analysis......................................................................196
3.3.2 Simple Differential Voltage Sense Amplifier.................................200
3.3.2.1 All-Transistor Sense Amplifier Circuit.............................200
3.3.2.2 AC Analysis......................................................................201
3.3.2.3 Transient Analysis............................................................203
3.3.3 Full-Complementary Differential Voltage Sense Amplifier...........207
3.3.3.1 Active Load Application...................................................207
3.3.3.2 Analysis and Design Considerations ................................209
3.3.4 Positive Feedback Differential Voltage Sense Amplifier..............211
3.3.4.1 Circuit Operation..............................................................211
3.3.4.2 Feedback Analysis............................................................213
3.3.5 Full-Complementary Positive-Feedback Differential
Voltage Sense Amplifier ................................................................217
3.3.6 Enhancements to Differential Voltage Sense Amplifiers ..............220
3.3.6.1 Approaches.......................................................................220
3.3.6.2 Decoupling Bitline Loads.................................................221
3.3.6.3 Feedback Separation.........................................................224
3.3.6.4 Current Sources................................................................226
3.3.6.5 Optimum Voltage-Swing to Sense Amplifie.r.s............. 229
3.4 Current Sense Amplifiers ...........................................................................232
3.4.1 Reasons for Current Sensing .........................................................232
3.4.2 Feedback Types and Impedances ...................................................236
3.4.3 Current-Mirror Sense Amplifier.....................................................238
3.4.4 Positive Feedback Current Sense Amplifier...................................240
viii CMOS Memory Circuits
3.4.4 Positive Feedback Current Sense Amplifier.....................................240
3.4.5 Current-Voltage Sense Amplifier.....................................................243
3.4.6 Crosscoupled Positive Feedback Current Sense Amplifier .............245
3.4.7 Negative Feedback Current Sense Amplifiers..................................249
3.4.8 Feedback Transfer Functions............................................................250
3.4.9 Improvements by Feedback..............................................................252
3.4.10 Stability and Transient Damping......................................................256
3.5 Offset Reduction..........................................................................................257
3.5.1 Offsets in sense Amplifiers..............................................................257
3.5.2 Offset Reducing Layout Designs......................................................259
3.5.3 Negative Feedback for Offset Decrease ...........................................260
3.5.4 Sample-and-Feedback Offset Limitation..........................................263
3.6 Nondifferential Sense Amplifiers.................................................................265
3.6.1 Basics...............................................................................................265
3.6.2 Common-Source Sense Amplifiers..................................................266
3.6.3 Common-Gate Sense Amplifers......................................................269
3.6.4 Common-Drain Sense Amplifiers....................................................273
Chapter 4. Memory Constituent Subcircuits............................. 277
4.1 Array Wiring................................................................................................278
4.1.1 Bitlines .............................................................................................278
4.1.1.1 Simple Models....................................................................278
4.1.1.2 Signal Limiters...................................................................283
4.1.2 Wordlines.........................................................................................287
4.1.2.1 Modelling ...........................................................................287
4.1.2.2 Signal Control.....................................................................290
4.1.3 Transmission Line Models...............................................................296
4.1.3.1 Signal Propagation and Reflections....................................296
4.1.1.2 Signal Transients................................................................301
4.1.4 Validity Regions of Transmission Line Models...............................308
4.2 Reference Circuits........................................................................................311
4.2.1 Basic Functions................................................................................311
4.2.2 Voltage References...........................................................................311
4.2.3 Current References...........................................................................318
4.2.4 Charge References............................................................................321
4.3 Decoders.......................................................................................................323
4.4 Output Buffers..............................................................................................328
4.5 Input Receivers.............................................................................................336
4.6 Clock Circuits...............................................................................................341
4.6.1 Operation Timing.............................................................................341
4.6.2 Clock Generators..............................................................................344
4.6.3 Clock Recovery................................................................................347
4.6.4 Clock Delay and Transient Control..................................................352
4.7 Power-Lines .................................................................................................355
4.7.1 Power Distribution...........................................................................355
4.7.2 Power-Line Bounce Reduction.........................................................359
Contents ix
Chapter 5. Reliability and Yield Improvement.........................................365
5.1 Reliability and Redundancy.......................................................................366
5.1.1 Memory Reliability........................................................................366
5.1.2 Redundancy Effects on Reliability.................................................369
5.2 Noises in Memory Circuits.........................................................................373
5.2.1 Noises and Noise Sources...............................................................373
5.2.2 Crosstalk Noises in Arrays.............................................................374
5.2.3 Crosstalk Reduction in Bitlines......................................................379
5.2.4 Power-Line Noises in Arrays .........................................................382
5.1.5 Thermal Noise................................................................................385
5.3 Charged Atomic Particle Impacts...............................................................388
5.3.1 Effects of Charged Atomic Particle Impacts ..................................388
5.3.2 Error Rate Estimate ........................................................................390
5.1.3 Error Rate Reduction......................................................................398
5.4 Yield and Redundancy ...............................................................................402
5.4.1 Memory Yield ................................................................................402
5.1.2 Yield Improvement by Redundancy Applications..........................406
5.5 Fault-Tolerance in Memory Designs..........................................................412
5.5.1 Faults, Failures, Errors and Fault-Tolerance ..................................412
5.5.2 Faults and Errors to Repair and Correct .........................................415
5.5.3 Strategies for Fault-Tolerance........................................................420
5.6 Fault Repair................................................................................................421
5.6.1 Fault Repair Principles in Memories..............................................421
5.6.2 Programming Elements..................................................................423
5.1.3 Row and Column Replacement......................................................428
5.1.4 Associative Repair..........................................................................434
5.1.5 Fault Masking.................................................................................436
5.7 Error Control Code Application in Memories............................................438
5.7.1 Coding Fundamentals.....................................................................438
5.7.2 Code Performance..........................................................................442
5.7.3 Code Efficiency..............................................................................446
5.7.4 Linear Systematic Codes................................................................453
5.7.4.1 Description .......................................................................453
5.7.4.2 Single Parity Check Code.................................................453
5.7.4.3 Berger Codes ....................................................................455
5.7.4.4 BCH Codes.......................................................................457
5.7.4.5 Binary Hamming Codes ...................................................457
5.7.4.6 Reed-Solomon (RS) Codes...............................................461
5.7.4.7 Bidirectional Codes..........................................................462
5.8 Combination of Error Control Coding and Fault-Repair............................464
Chapter 6. Radiation Effects and Circuit Hardening.................................469
6.1 Radiation Effects ......................................................................470
6.1.1 Radiation Environments.................................................................470
6.1.2 Permanent Ionization Total-Dose Effects......................................471
6.1.3 Transient Ionization Dose-Rate Effects.........................................475
x CMOS Memory Circuits
6.1.4 Fabrication-Induced Radiations and Neutron Fluence.................... 477
6.1.5 Combined Radiation Effects.............................................................478
6.2 Radiation Hardening....................................................................................481
6.2.1 Requirements and Hardening Methods............................................481
6.2.2 Self-Compensation and Voltage Limitation in Sense Circuits........486
6.2.3 Parameter Tracking in Reference Circuits........................................491
6.2.4 State Retention in Memory Cells......................................................493
6.2.5 Self-Adjusting Logic Gates..............................................................495
6.2.6 Global Fault-Tolerance for Radiation Hardening.............................499
6.3 Designing Memories in CMOS SOI (SOS).............................. 501
6.3.1 Basic Considerations.........................................................501
6.3.1.1 Devices.............................................................501
6.3.1.2 Features.................................................................505
6.3.2 Floating Substrate Effects........................................................509
6.3.2.1 History Dependency, Kinks and Passgate Leakages............509
6.3.2.2 Relieves.................................................516
6.3.3 Side- and Back-Channel Effects......................................520
6.3.3.1 Side-Channel Leakages, Kinks and Breakdowns.............520
6.3.3.2 Back-Channel- and Photocurrents................................524
6.3.3.3 Allays..................................................................................526
6.3.4 Diode-Like Nonlinear Parasitic Elements and Others.....................527
References .............................................................................531
Index .................................................................................................541
Preface
Staggering are both the quantity and the variety of complementary-
metal-oxide-semiconductor CMOS memories. CMOS memories are traded
as mass-products world wide, and are diversified to satisfy nearly all
practical requirements in operational speed, power, size and environmental
tolerance. Without the outstanding speed, power and packing-density
characteristics of CMOS memories neither personal computing, nor space
exploration, nor superior defense-systems, nor many other feats of human
ingenuity could be accomplished. Electronic systems need continuous
improvements in speed performance, power consumption, packing den-
sity, size, weight and costs; and these needs spur the rapid advancement of
CMOS memory processing and circuit technologies.
The objective of this book is to provide a systematic and comprehensive
insight which aids the understanding, practical use and progress of CMOS
memory circuits, architectures and design techniques. In the area of
semiconductor memories, since 1977 this is the first and only book that is
devoted to memory circuits. Besides filling the general void in memory-
related works, so far this book is the only one that covers inclusively such
modern and momentous issues in CMOS memory designs as sense
amplifiers, redundancy implementations and radiation hardening, and dis-
closes practical approaches to combine high performance, and reliability,
with high packing density and yield by circuit-technological and architec-
tural means.