Table Of ContentCMOS LOGIC CIRCUIT DESIGN
CMOS LOGIC CIRCUIT DESIGN
John P. Uyemura
Georgia Institute of Technology
KLUWER ACADEMIC PUBLISHERS
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Dedication
This book is dedicated to
Christine and Valerie
for all ofthe joy and happiness
that they bring into my life
Preface
This book is based on the earlier Kluwer title Circuit Design for CMOS/VLSI
which was published in 1992. At that time, CMOS was just entering the main-
stream as a technique for high-speed, high-density logic circuits. Although the
technology had been invented in the 1960’s, it was still necessary to include Sec-
tion 1.1 entitled Why CMOS? to justify a book on the subject. Since that time,
CMOS has matured and taken its place as the primary technology for VLSI and
ULSI digital circuits. It therefore seemed appropriate to update the book and gen-
erate a second edition.
Background of the Book
After loading the old files and studying the content of the earlier book, it became clear to me that
the field is much more stable and well-defined than it was in the early 1990’s. True, technological
advances continue to make CMOS better and better, but the general foundations of modern digital
circuit design have not changed much in the past few years. New logic circuit techniques appearing
in the literature are based on well-established ideas, indicating that CMOS has matured.
As a result of this observation, the great majority of the old files were abandoned and replaced
with expanded discussions and new topics, and the book was reorganized to the form described
below. There are sections that didn’t change much. For example, Chapter 1 (which introduces
MOSFETs) includes more derivations and pedagogical material, but the theme is about the same.
But, many items are significantly different. For example, the earlier book contained about 60 pages
on dynamic logic circuits. The present volume has almost three times the number of pages dedi-
cated to this important area. In addition, the book has been written with more of a textbook flavor
and includes problem sets.
Contents
Chapter 1 introduces the MOS system and uses the gradual-channel approximation to derive the
square-law equations and basic FET models. This sets the notation for the rest of the book. Bulk-
charge models are also discussed, and the last part of the chapter introduces topics from small-
device theory, such as scaling and hot electrons.
viii
Chapter 2 is an overview of silicon fabrication and topics relevant to a CMOS process flow.
Basic ideas in lithography and pattern transfer are covered, as are items such as design rules, FET
sizing, isolation, and latch-up. This chapter can be skipped in a first reading, but it is important to
understanding some problems that are specific to layout and fabrication issues. It is not meant to
replace a dedicated course in the subject.
Circuit design starts in Chapter3, which is a detailed analysis of the static CMOS inverter. The
study is used to set the stage for all of the remaining chapters by defining important DC quantities,
transient times, and introducing CMOS circuit analysis techniques. Chapter 4 concentrates on a
detailed study of the electrical characteristics of FETs when used as voltage-controlled electronic
switches. In particular, the treatment is structured to emphasize the strong and weak points of
nFETs and pFETs, and how both are used to create logic networks. This feeds into Chapter 5,
which is devoted entirely to static logic gates. This includesfully complementarydesigns in addi-
tion to variants such as pseudo-nMOS circuits and novel XOR/XNOR networks. Chapter 6 on
transmission gate logic completes this part of the book.
Dynamic circuit concepts are introduced in Chapter 7. This chapter includes topics such as
charge sharing and charge leakage in various types of CMOS circuit arrangements. RC modelling
is introduced, and the Elmore formulas for the time constant of an RC ladder is derived. Clocks are
introduced and used in various types of clocked static and dynamic circuits. Dynamic logic families
are presented in Chapter8. The discussion includes detailed treatments ofprecharge/evaluate rip-
ple logic, domino logic cascades, self-resetting logic gates, single-phase circuits and others. I have
tried to present the material in an order that demonstrates how the techniques were developed to
solve specific problems. Chapter 9 deals with differential dual-rail logic families such as CVSL
and CPL with short overviews of related design styles.
The material in Chapter 10 is concerned with selected topics in chip design, such as intercon-
nect modelling and delays, crosstalk, BSD-protected input circuits, and the effects of transmission
lines on output drivers. The level of the presentation in this chapter is reasonably high, but the top-
ics are complex enough so that the discussions only graze the surface. It would take another volume
(at least) to do justice to these problems. As such, the chapter was included to serve as an introduc-
tion for other courses or readings.
Use as a Text
There is more than enough material in the book for a 1-semester or 2-quarter sequence at the senior
undergraduate or the first-year graduate level. The text itself is structured around a first-year gradu-
ate course entitled Digital MOS Integrated Circuits that is taught at GeorgiaTech every year. The
course culminates with each student completing an individualdesign project.
My objectives in developing the course material are two-fold. First, I want the students to be
able to read relevant articles in the IEEE Journal ofSolid-State Circuits with a reasonable level of
comprehension by the end of the course. The second objective is more pragmatic. I attempt to
structure the content and depth of the presentation to the point where the students can answer all of
the questions posed in their job interviews and plant visits, and secure positions as chip designers
after graduation. Moreover, I try to merge basics with current design techniques so that they can
function in theirpositions with only a minimum amount of start-up time.
Problem sets have been provided at the end of every chapter (except Chapter 2). The questions
are based on the material emphasized in the chapter, and most of them are calculational in nature.
Process parametershave been provided, but these can easily be replaced by different sets that might
be of special interest. Most of the problems have appeared on my homeworks or exams; others are
questions that I wrote, but never got around to using for one reason or another. I have tried to
include a reasonable number of problems without getting excessive. Students that can follow the
level of detail used in the book should not have many problems applying the material. SPICE sim-
ulations add a lot to understanding, and should be performedwhenever possible.
ix
Apologies
No effort was made to include a detailed list of references in the final version of the book. I initially
set out to compile a comprehensive bibliography. However, after several graduate students per-
formed on-line literature searches that yielded results far more complete than my list, I decided to
includeonly a minimal set here. The references that were chosen are books and a few papers whose
contents are directly referenced in the writing. The task is thus left to the interestedreader.
I have tried very hard to eliminate the errors in the book, but realize that many will slip through.
After completing six readings of the final manuscript, I think that I caught most of the major errors
and hope that the remaining ones are relatively minor in nature. I apologize in advance for those I
missed.
Acknowledgments
Many thanks are due to Carl Harris of Kluwer who has shown amazing patience in waiting for this
project to be completed. He never seemed to lose hope, even when I was quite ill (and crabby) for
several months and unable to do much. Of course, those who know Carl will agree with me that he
is a true gentlemen with exceptional qualities. And a real nice guy.
Dr. Roger P. Webb, Chair of the School of Electrical & ComputerEngineering at GeorgiaTech,
has always supported my efforts in writing, and has my never ending thanks. Dr. William (Bill)
Sayle, Vice-Chair for ECE Undergraduate Affairs, has also helped me more times than I can count
during the many years we have known each other. I am grateful to my colleagues that have taken
the time to discuss technical items with me. On the current project, this includes Dr. Glenn S.
Smith, Dr. Andrew F. Peterson, and Dr. David R. Hertling in particular.
I am grateful to the reviewers that took the time to weed through early versions of the manu-
script that were full of typos, missing figures, and incomplete sections to give me their comments.
Feedback from the many students and former students that have suffered through the course have
helped shape the contents and presentation.
Finally, I would like to thank my wife Melba and my daughtersValerie and Christine that have
put up with dad sitting in front of the computer for hours and hours and hours. Their love has kept
me going through this project and life in general!
John P. Uyemura
Smyrna, Georgia
Table of Contents
Preface vii
Table of Contents xi
Chapter1
Physics and Modelling
of MOSFETs 1
1.1 Basic MOSFET Characteristics 1
1.1.1 The MOS Threshold Voltage 3
1.1.2 Body Bias 9
1.2 Current-Voltage Characteristics 10
1.2.1 Square-Law Model 14
1.2.2 Bulk-Charge Model 18
1.2.3 The Role of Simple Device Models 19
1.3 p-Channel MOSFETs 19
1.4 MOSFET Modelling 22
1.4.1 Drain-Source Resistance 23
1.4.2 MOSFET Capacitances 24
1.4.3 Junction Leakage Currents 35
1.4.4 Applications to Circuit Design 37
1.5 Geometric Scaling Theory 37
1.5.1 Full-Voltage Scaling 40
1.5.2 Constant-Voltage Scaling 43
1.5.3 Second-Order Scaling Effects 44
1.5.4 Applications of Scaling Theory 44
1.6 Small-Device Effects 45
1.6.1 Threshold Voltage Modifications 45
1.6.2 Mobility Variations 50
1.6.3 Hot Electrons 52
1.7 Small Device Model 53
1.8 MOSFET Modelling in SPICE 56
1.8.1 Basic MOSFET Model 56
xii
1.9 Problems 58
1.10 References 59
Chapter 2
Fabrication and Layout
of CMOS Integrated Circuits 61
2.1 Overview of Integrated Circuit Processing 61
2.1.1 Oxides 61
2.1.2 Polysilicon 63
2.1.3 Doping and Ion Implantation 64
2.1.4 Metal Layers 67
2.2 Photolithography 68
2.3 The Self-Aligned MOSFET 71
2.3.1 The LDD MOSFET 72
2.4 Isolation and Wells 73
2.4.1 LOCOS 74
2.4.2 Improved LOCOS Process 77
2.4.3 Trench Isolation 78
2.5 The CMOS Process Flow 78
2.5.1 Silicide Structures 83
2.5.2 Other Bulk Technologies 83
2.6 Mask Design and Layout 85
2.6.1 MOSFET Dimensions 88
2.6.2 Design Rules 90
2.6.3 Types of Design Rules 90
2.6.4 General Comments 94
2.7 Latch-Up 94
2.7.1 Latch up Prevention 97
2.8 Defects and Yield Considerations 99
2.8.1 Other Failure Modes 100
2.9 Chapter Summary 101
2.10 References 102
xiii
Chapter 3
The CMOS Inverter:
Analysis and Design 103
3.1 Basic Circuit and DC Operation 103
3.1.1 DC Characteristics 106
3.1.2 Noise Margins 109
3.1.3 Layout Considerations 112
3.2 Inverter Switching Characteristics 113
3.2.1 Switching Intervals 114
3.2.2 High-to-Low Time 115
3.2.3 Low-to-High Time 117
3.2.4 Maximum Switching Frequency 118
3.2.5 Transient Effects on the VTC 119
3.2.6 RC Modelling 120
3.2.7 PropagationDelay 122
3.2.8 Use of the Step-Input Waveform 124
3.3 Output Capacitance 125
3.4 Inverter Design 134
3.4.1 DC Design 134
3.4.2 Transient Design 137
3.5 Power Dissipation 140
3.6 Driving Large Capacitive Loads 144
3.7 Problems 152
3.8 References 154
Chapter 4
Switching Properties
of MOSFETs 155
4.1 nFET Pass Transistors 155
4.1.1 Logic 1 Input 156
4.1.2 Logic 0 Input 158
4.1.3 Switching Times 159
4.1.4 Interpretation of the Results 159
4.1.5 Layout 161
4.2 pMOS Transmission Characteristics 163
4.2.1 Logic 0 Input 163
