Circuits and Algorithms for Pipelined ADCs in Scaled CMOS Technologies Lane Gearle Brooks

184 Pages·2009·13.42 MB·English

Circuits and Algorithms for Pipelined ADCs in
Scaled CMOS Technologies
by
Lane Gearle Brooks
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy in Computer Science and Engineering
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June 2008
c Massachusetts Institute of Technology 2008. All rights reserved.
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Author ..............................................................
Department of Electrical Engineering and Computer Science
May 6, 2008
Certified by..........................................................
Hae-Seung Lee
Professor
Thesis Supervisor
Certified by..........................................................
Gregory Wornell
Professor
Thesis Supervisor
Accepted by.........................................................
Terry P. Orlando
Chairman, Department Committee on Graduate Students
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Circuits and Algorithms for Pipelined ADCs in Scaled
CMOS Technologies
by
Lane Gearle Brooks
Submitted to the Department of Electrical Engineering and Computer Science
on May 6, 2008, in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy in Computer Science and Engineering
Abstract
CMOS technology scaling is creating significant issues for analog circuit design. For
example, reduced signal swing and device gain make it increasingly difficult to realize
high-speed, high-gain feedback loops traditionally used in switched capacitor circuits.
Thisresearchinvolvestwocomplementarymethodsforaddressingscalingissues. First
isthedevelopmentoftwoblinddigitalcalibrationtechniques. DecisionBoundaryGap
Estimation (DBGE) removes static non-linearities and Chopper Offset Estimation
(COE) nulls offsets in pipelined ADCs. Second is the development of circuits for a
new architecture called zero-crossing based circuits (ZCBC) that is more amenable
to scaling trends. To demonstrate these circuits and algorithms, two different ADCs
were designed: an 8 bit, 200MS/s in TSMC 180nm technology, and a 12 bit, 50 MS/s
in IBM 90nm technology. Together these techniques can be enabling technologies for
bothpipelinedADCsandgeneralmixedsignaldesignindeepsub-microntechnologies.
Thesis Supervisor: Hae-Seung Lee
Title: Professor
Thesis Supervisor: Gregory Wornell
Title: Professor
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Acknowledgments
I would like to thank my advisers, family, and friends for helping and supporting me
with this work.
I would like to thank NDSEG, CICS, and DARPA for funding my research.
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Contents
1 Introduction 19
1.1 Pipelined ADC Overview . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2 Comparator Based Switched Capacitor Circuits . . . . . . . . . . . . 26
1.3 Pipelined ADC Error Models . . . . . . . . . . . . . . . . . . . . . . 27
1.3.1 Finite Opamp Gain . . . . . . . . . . . . . . . . . . . . . . . . 27
1.3.2 Finite Current Source Output Impedance . . . . . . . . . . . . 28
1.3.3 Capacitor Mismatch . . . . . . . . . . . . . . . . . . . . . . . 31
1.3.4 Charge Injection and Stage Offset . . . . . . . . . . . . . . . . 32
1.3.5 Bit Decision Comparator Offset . . . . . . . . . . . . . . . . . 32
1.3.6 Errors from Multiple Stages . . . . . . . . . . . . . . . . . . . 33
1.4 Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2 Decision Boundary Gap Estimation 39
2.1 Gap Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.2 Gap Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.2.1 Max-Min Gap Estimator . . . . . . . . . . . . . . . . . . . . . 46
2.2.2 Bin-Reshaping Gap Estimator . . . . . . . . . . . . . . . . . . 48
2.2.3 Cost-Minimizing Estimator . . . . . . . . . . . . . . . . . . . 51
2.2.4 Estimator Discussion . . . . . . . . . . . . . . . . . . . . . . . 55
2.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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3 Zero-Crossing Based Circuits 61
3.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.1.1 Opamp-Based Switch Capacitor Circuits . . . . . . . . . . . . 61
3.1.2 Comparator-Based Switched Capacitor Circuits . . . . . . . . 62
3.2 Zero-Crossing Based Circuits . . . . . . . . . . . . . . . . . . . . . . . 64
3.3 ZCBC Pipelined ADC Implementation . . . . . . . . . . . . . . . . . 67
3.3.1 DZCD Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.3.2 Current Source Splitting . . . . . . . . . . . . . . . . . . . . . 68
3.3.3 Shorting Switches . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.3.4 Reference Voltage Switches . . . . . . . . . . . . . . . . . . . . 70
3.3.5 Current Source Implementation . . . . . . . . . . . . . . . . . 71
3.3.6 Bit Decision Flip-Flops . . . . . . . . . . . . . . . . . . . . . . 72
3.3.7 First Stage Considerations . . . . . . . . . . . . . . . . . . . . 73
3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.5 Power Efficiency Analysis . . . . . . . . . . . . . . . . . . . . . . . . 76
3.5.1 DZCD Noise Analysis . . . . . . . . . . . . . . . . . . . . . . 76
3.5.2 Comparison to Original CBSC Implementation . . . . . . . . 84
3.5.3 FOM Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4 Chopper Offset Estimation 89
4.1 Chopper Offset Estimation . . . . . . . . . . . . . . . . . . . . . . . . 92
4.1.1 Traditional Chopper Stabilization . . . . . . . . . . . . . . . . 92
4.1.2 Chopper Offset Estimation (COE) . . . . . . . . . . . . . . . 93
4.1.3 COE Decimation . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.2 Random Chopping Vector . . . . . . . . . . . . . . . . . . . . . . . . 96
4.2.1 Minimum Variance Linear Unbiased Estimator . . . . . . . . . 97
4.2.2 MVLU Performance . . . . . . . . . . . . . . . . . . . . . . . 99
4.2.3 MVLU Example . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2.4 Distortion Performance . . . . . . . . . . . . . . . . . . . . . . 101
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4.2.5 Random vs. Deterministic Chopping . . . . . . . . . . . . . . 102
4.3 Additional COE Architectures . . . . . . . . . . . . . . . . . . . . . . 103
4.3.1 Input Referred Offset Compensation with COE . . . . . . . . 104
4.3.2 COE for Pipelined ADCs . . . . . . . . . . . . . . . . . . . . . 105
4.3.3 Per-Stage COE for Pipelined ADCs . . . . . . . . . . . . . . . 106
4.3.4 Multistage Chopping . . . . . . . . . . . . . . . . . . . . . . . 108
4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5 ZCBC Revisited 111
5.1 System Level Improvements . . . . . . . . . . . . . . . . . . . . . . . 111
5.1.1 Embedded SRAM and Programmable Output Drivers . . . . . 112
5.1.2 Triple Well for Improved Substrate Isolation . . . . . . . . . . 112
5.1.3 On-chip Bias and Voltage Generation . . . . . . . . . . . . . . 112
5.1.4 Single Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.1.5 Packaging Considerations . . . . . . . . . . . . . . . . . . . . 115
5.2 Fully Differential ZCBC . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.2.1 Common Mode Control . . . . . . . . . . . . . . . . . . . . . 118
5.2.2 Symmetry for Improved Power Supply Noise Rejection . . . . 119
5.2.3 Differential Zero-Crossing Detector . . . . . . . . . . . . . . . 122
5.2.4 Chopper Offset Estimation . . . . . . . . . . . . . . . . . . . . 124
5.3 Voltage References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3.1 Off-chip Reference Voltage Issues . . . . . . . . . . . . . . . . 126
5.3.2 Voltage Reference Switching via Capacitor Splitting . . . . . . 128
5.3.3 Capacitor Splitting with Fully Differential Designs . . . . . . . 132
5.4 Redundancy For Increased Signal Range . . . . . . . . . . . . . . . . 135
5.5 Complete ZCBC Pipeline Stage . . . . . . . . . . . . . . . . . . . . . 139
5.6 Sub-ADC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.6.1 Bit Decision Comparator Design . . . . . . . . . . . . . . . . . 145
5.7 Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.7.1 Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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5.7.2 Input Referred Noise Derivation . . . . . . . . . . . . . . . . . 150
5.7.3 Substituting Real Circuit Parameters . . . . . . . . . . . . . . 154
5.7.4 Linearity from Finite Current Source Impedance . . . . . . . . 156
5.7.5 Differential ZCD Design Methodology . . . . . . . . . . . . . . 157
5.7.6 Number of Ramps Analysis . . . . . . . . . . . . . . . . . . . 161
5.8 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.8.1 Overall Performance . . . . . . . . . . . . . . . . . . . . . . . 163
5.8.2 ZCD Offset Performance . . . . . . . . . . . . . . . . . . . . . 164
5.8.3 I/O Noise Coupling . . . . . . . . . . . . . . . . . . . . . . . . 167
5.8.4 BDC Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6 Conclusion 171
6.1 ZCBC Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.1.1 Reference Voltages . . . . . . . . . . . . . . . . . . . . . . . . 171
6.1.2 PVT Hardening . . . . . . . . . . . . . . . . . . . . . . . . . . 173
6.1.3 Common Mode Feedback . . . . . . . . . . . . . . . . . . . . . 175
6.2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
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