Circuit Design for RF Transceivers

350 Pages·2001·6.29 MB·English

by  Domine M.W. Leenaerts

CIRCUIT DESIGN FORRFTRANSCEIVERS
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CIRCUIT DESIGN
FOR
RF TRANSCEIVERS
By
Domine Leenaerts
Philips Research Laboratories Eindhoven
Johan van der Tang
Eindhoven University of Technology
and
Cicero S. Vaucher
Philips Research Laboratories Eindhoven
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON, DORDRECHT, LONDON, MOSCOW
eBookISBN: 0-306-47978-8
Print ISBN: 0-7923-7551-3
©2003 Kluwer Academic Publishers
NewYork, Boston, Dordrecht, London, Moscow
Print ©2001 Kluwer Academic Publishers
Dordrecht
All rights reserved
No part of this eBook maybe reproducedor transmitted inanyform or byanymeans,electronic,
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
Visit Kluwer Online at: http://kluweronline.com
and Kluwer's eBookstore at: http://ebooks.kluweronline.com
To Lisanne, Nienke, and Viviane
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Contents
Preface xiii
1. RF DESIGN: CONCEPTS AND TECHNOLOGY 1
1.1 RF Specifications 1
1.1.1 Gain 2
1.1.2 Noise 6
1.1.3 Non-linearity 10
1.1.4 Sensitivity 14
1.2 RF Device Technology 14
1.2.1Characterization and Modeling 15
Modeling 15
Cut-off Frequency 17
Maximum Oscillation Frequency 20
Input Limited Frequency 21
Output Limited Frequency 22
Maximum Available Bandwidth 23
1.2.2 Technology Choice 23
Double Poly Devices 24
Silicon-on-Anything 26
Comparison 28
SiGe Bipolar Technology 30
RF CMOS 30
1.3 Passives 33
1.3.1 Resistors 34
1.3.2 Capacitors 35
1.3.3 Planar Monolithic Inductors 37
References 42
2. ANTENNAS, INTERFACE AND SUBSTRATE 43
2.1 Antennas 43
2.2 Bond Wires 46
2.3 Transmission Lines 49
2.3.1 General Theory 49
2.3.2 Impedance Matching using Transmission Lines 51
2.3.3 Microstrip Lines and Coplanar Lines 54
2.4 Bond Pads and ESD Devices 58
vii
viii CIRCUIT DESIGN FOR RF TRANSCEIVERS
2.4.1 Bond Pads 59
2.4.2 ESD Devices 60
ggNMOST ESD Device 61
pn and np-Diode ESD Device 64
2.5 Substrate 67
2.5.1 Substrate Bounces 69
2.5.2 Design Techniques to Reduce the Substrate Bounces 71
References 77
3. LOW NOISE AMPLIFIERS 79
3.1 Specification 79
3.2 Bipolar LNA design for DCS Application in SOA 84
3.2.1 Design of the LNA 84
3.2.2 Measurements 93
3.3 CMOS LNA Design 94
3.3.1 Single Transistor LNA 94
Design Steps 95
Simulation and Measurement 101
3.3.2 Classical LNA Design 104
The Design 105
Measurement Results 108
3.4 Evaluation 108
References 111
4. MIXERS 113
4.1 Specification 113
4.2 Bipolar Mixer Design 118
4.3 CMOS Mixers 121
4.3.1 Active CMOS Mixers 122
4.3.2 Passive CMOS Mixers 127
1/f-Noise in Mixer Transistors 128
1/f-Noise due to IF Amplifier 133
1/f-Noise due to Switched-Capacitor Behavior 138
4.3.3 Concluding Remarks 141
References 142
5. RF POWER AMPLIFIERS 145
5.1 Specification 145
5.1.1 Efficiency 145
5.1.2 Generic Amplifier Classes 146
5.1.3 Heating 149
Contents ix
5.1.4 Linearity 150
5.1.5 Ruggedness 151
5.2 Bipolar PA Design 151
5.3 CMOS PA Design 160
5.4 Linearization Principles 166
5.4.1 Predistortion Technique 168
5.4.2 Phase-Correcting Feedback 172
5.4.3 Envelope Elimination and Restoration (EER) 177
5.4.4 Cartesian Feedback 180
References 182
6. OSCILLATORS 185
6.1 Introduction 185
6.1.1 The Ideal Oscillator 185
6.1.2 The Non-ideal Oscillator 186
6.1.3 Application and Classification 188
6.1.4 Oscillation Conditions 191
6.1.5 Amplitude Stabilization 196
6.2 Specifications 199
6.2.1 Frequency and Tuning 199
6.2.2 Tuning Constant and Linearity 200
6.2.3 Power Dissipation 200
6.2.4 Phase Noise to Carrier Ratio 201
Reciprocal Mixing 202
Signal to Noise Degradation of FM Signals 203
Spurious Emission 203
6.2.5 Harmonics 204
6.2.6 I/Q Matching 204
6.2.7 Technology and Chip Area 205
6.3 LC Oscillators 206
6.3.1 Frequency, Tuning and Phase Noise 206
Frequency 207
Tuning 208
Phase Noise to Carrier Ratio 209
6.3.2 Topologies 221
6.4 RC Oscillators 223
6.4.1 Frequency, Tuning and Phase Noise 223
Frequency 224
Tuning 225
Phase Noise to Carrier Ratio 228
6.4.2 Topologies 229