CALIFORNIA STATE UNIVERSITY, NORTHRIDGE DESIGN AND MODELING OF AN ANALOG TO ...

98 Pages·2013·1.96 MB·English

by  Herwies, Riayad M

CALIFORNIA STATE UNIVERSITY, NORTHRIDGE

DESIGN AND MODELING OF AN ANALOG TO DIGITAL CONVERTER USING FPGA
BOARD

A graduate project submitted in partial fulfillment of the requirements
For the degree of Master of Science in
Electrical Engineering

By
Riayad M Herwies

December 2013
The graduate project of Riayad Herwies is approved:

Professor. Benjamin F. Mallard Date

Dr. Somnath Chattopadhyay Date

Dr. Nagi El Naga, Chair Date

California State University, Northridge

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Acknowledgements
First of all, I would like to thank Dr. El Naga who has guided me in this project and provided
help and valuable feedback. Also, I would like to express my respect and gratitude to Professor.
Mallard and Dr. Chattopadhyay for agreeing to serve on the committee.

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Table of Contents
Signature page……………………………………………………………………………..………………..ii
Acknowledgements ...................................................................................................................................... iii
List of Figures .............................................................................................................................................. ix
ABSTRACT ................................................................................................................................................ xii
Chapter 1 Introduction .................................................................................................................................. 1
1.1 The objective of the project .......................................................................................................... 3
1.2 Organization of the Project ................................................................................................................. 3
Chapter 2 Analog to Digital Characteristics ................................................................................................. 4
2.1 Acquisition Time ................................................................................................................................ 5
2.2 Aliasing ............................................................................................................................................... 5
2.3 Aperture Delay .................................................................................................................................... 5
2.5 Binary Coding (Unipolar) ................................................................................................................... 7
2.6 Bipolar Inputs...................................................................................................................................... 7
2.7 Crosstalk ............................................................................................................................................. 7
2.8 Integral Nonlinearity (INL) ................................................................................................................. 7
2.9 Differential Nonlinearity (DNL) ......................................................................................................... 8
2.10 Full-Power Bandwidth (FPBW)........................................................................................................ 9
2.11 Offset and Gain Error ........................................................................................................................ 9
2.12 Full-Scale (FS) error ....................................................................................................................... 10
2.13 FS Gain-Error (DACs) .................................................................................................................... 11
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2.14 Gain Error Drift ............................................................................................................................... 11
2.15 Full-Scale (FS) error ....................................................................................................................... 11
2.16 Gain Matching ................................................................................................................................ 12
2.17 Major-Carry Transition ................................................................................................................... 12
2.18 Glitch Impulse ................................................................................................................................. 12
2.20 Small-Signal Bandwidth (SSBW) ................................................................................................... 12
2.21 Spurious-Free Dynamic Range (SFDR) ......................................................................................... 13
2.22 Signed Binary Coding ..................................................................................................................... 13
2.23 Transition Noise .............................................................................................................................. 13
2.24 Two's Complement Coding ............................................................................................................. 14
2.25 Monotonic ....................................................................................................................................... 14
2.26 No Missing Codes ........................................................................................................................... 14
2.27 Aperture Error ................................................................................................................................. 14
2.28 Sampling Rate/Frequency ............................................................................................................... 14
2.29 Settling Time ................................................................................................................................... 15
2.30 Signal-to-Noise and Distortion (SINAD) ....................................................................................... 15
2.31 Total Harmonic Distortion (THD) .................................................................................................. 15
2.32 Dynamic Range ............................................................................................................................... 15
2.33 Effective Number of Bits (ENOB) .................................................................................................. 16
2.34 Least Significant Bit (LSB) ............................................................................................................ 16
2.35 Nyquist Frequency .......................................................................................................................... 16
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2.36 Oversampling .................................................................................................................................. 16
2.37 Undersampling ................................................................................................................................ 16
2.38 Quantization Error .......................................................................................................................... 17
2.39 Resolution ....................................................................................................................................... 17
2.40 Signals-to-Noise Ratio (SNR) ......................................................................................................... 17
2.41 Sample-and-Hold (S/H) Characteristics .......................................................................................... 17
2.42 ADCs Tradeoff ................................................................................................................................ 19
Chapter 3 Different Types of Conversion ................................................................................................... 20
3.1 Flash ADC ........................................................................................................................................ 20
3.2 Pipeline ADC .................................................................................................................................... 22
3.3 Successive Approximation ADC ...................................................................................................... 22
3.4 Integrating ADC ................................................................................................................................ 24
3.5 Oversampling ADC .......................................................................................................................... 25
3.5.1 First Order Sigma/Delta Modulator .......................................................................................... 26
3.5.2 The Higher Order Sigma/Delta Modulator ................................................................................ 27
3.6 ADCs comparison ............................................................................................................................. 28
3.6.1 Successive Approximation ADC vs. Pipelined ADC ................................................................ 28
3.6.2 Successive Approximation ADC vs. Flash ADC ....................................................................... 28
3.6.3 Successive Approximation ADC vs. Sigma/Delta ADC ........................................................... 29
3.6.4 Pipeline ADC vs. Flash ADC .................................................................................................... 29
3.6.5 Pipeline ADC vs. Half- (Two-Step) Flash ADC ........................................................................ 30
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3.6.6 Pipeline ADC vs. Sigma/Delta ADC ......................................................................................... 30
3.6.7 Integrating ADC vs. Successive Approximation ADC .............................................................. 31
3.6.8 Integrating ADC vs. Sigma/Delta ADC ..................................................................................... 31
3.6.9 Flash ADC vs. Integrating ADC ................................................................................................ 32
3.6.10 Flash ADC vs. Sigma/Delta ADC ............................................................................................ 32
3.7 Choosing the Right ADC .................................................................................................................. 32
Chapter 4 Hardware Design ........................................................................................................................ 36
4.1 Spartan 3E FPGA .............................................................................................................................. 36
4.2 Hardware Design: ............................................................................................................................. 37
4.3 Low Voltage Differential Signaling (LVDS):................................................................................... 38
4.4 Comparator: ...................................................................................................................................... 39
4.5 Digital to Analog Converter (DAC): ................................................................................................ 40
4.5.1 Sigma/Delta DAC: ..................................................................................................................... 40
4.5.2 Pulse Width Modulator (PWM): ................................................................................................ 41
4.6 Filters: ............................................................................................................................................... 42
4.6.1 Finite Impulse Response Filter (FIR): ....................................................................................... 42
4.6.2 Cascaded Integrator Comb Filter (CIC): .................................................................................... 44
4.7 Implementing Sigma/Delta ADC in FPGA: ..................................................................................... 44
4.8 Implementing Single-Slope ADC on FPGA: .................................................................................... 46
4.8.1 Fine Measurement: ..................................................................................................................... 47
4.9 Different Designs of Single-Slope ADC: .......................................................................................... 49
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Chapter 5 Design Implementation and Simulation ..................................................................................... 52
5.1 Error Finder ....................................................................................................................................... 52
5.2 TDC using Error Finder .................................................................................................................... 53
5.3 Double ring controllable oscillator ................................................................................................... 56
5.4 Delay Locked Loop (DLL) ............................................................................................................... 57
5.5 Slow and Fast Clock Generating Using Ring Oscillator ................................................................... 59
5.6 Phase Detector .................................................................................................................................. 60
5.7 8-bit Binary Counter ......................................................................................................................... 62
5.8 Time to Digital Converter (TDC) ..................................................................................................... 63
5.9 First Design of Single-Slope ADC .................................................................................................... 66
5.9.1 Pulse Width Modulator (PWM) as a DAC .................................................................................... 69
5.9.2 Sigma/Delta DAC .......................................................................................................................... 70
5.10 Second Design of Single-Slope ADC ............................................................................................. 72
5.11 Third Design of Single-Slope ADC ................................................................................................ 75
Chapter 6 Conclusion .................................................................................................................................. 79
References ................................................................................................................................................... 81

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List of Figures
Figure 1-1 : (a) Analog to Digital Conversion (b) Digital to Analog Conversion ........................................ 1
Figure 2-1: Analog to Digital and Digital To Analog Conversion ............................................................... 4
Figure 2-2 : Aperture delay (red) and jitter (blue) ........................................................................................ 6
Figure 2-3: Aperture Jitter ............................................................................................................................ 6
Figure 2-4: Integral Nonlinearity (INL) ........................................................................................................ 8
Figure 2-5: Differential nonlinearity (DNL) ................................................................................................. 9
Figure 2-6: Offset and Gain Errors ............................................................................................................. 10
Figure 2-7 : Full-scale error for an ADC and a DAC ................................................................................. 11
Figure 2-8 : Code Transition Noise............................................................................................................. 13
Figure 2-9 : A simplified sample and hold circuit diagram. ....................................................................... 18
Figure 2-10 : Track and Hold ...................................................................................................................... 18
Figure 3-1: Flash ADC ................................................................................................................................ 21
Figure 3-2 : Two-Step Flash ADC .............................................................................................................. 21
Figure 3-3 : Pipeline ADC .......................................................................................................................... 22
Figure 3-4 : Successive Approximation ADC ............................................................................................ 23
Figure 3-5 : Successive Approximation DAC ............................................................................................ 23
Figure 3-6 : Single-Slope ADC ................................................................................................................... 24
Figure 3-7 : (a) ADC Comparator Output (b) Counted Pulses During the Integrator Time. ...................... 25
Figure 3-8 : Dual Slope ADC ..................................................................................................................... 25
Figure 3-9 : (a) Sampling frequency at twice the signal bandwidth (b) Aliasing (c) Oversampling .......... 26
Figure 3-10 : 1st Order Sigma/Delta ADC .................................................................................................. 27
Figure 3-11 : The higher order Sigma/Delta Modulator ............................................................................. 27
Figure 3-12 : ADCs Applications ............................................................................................................... 32
Figure 4-1 : Spartan-3E FPGA.................................................................................................................... 36
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Figure 4-2 : The Hardware Design of the Digital ADC .............................................................................. 37
Figure 4-3 : Low Voltage Differential Signaling (LVDS) .......................................................................... 38
Figure 4-4 : Rising and Falling Waveforms for a LVDS Output Buffer .................................................... 38
Figure 4-5 : Comparator (1-bit ADC) ......................................................................................................... 39
Figure 4-6 : The Input and The Output of the 1-bit ADC ........................................................................... 39
Figure 4-7 : DAC Structure ......................................................................................................................... 40
Figure 4-8 : Pulse Width Modulator ........................................................................................................... 41
Figure 4-9 : Filtering the pulses to get the output sinwave ......................................................................... 42
Figure 4-10 : Block Diagram of FIR filter .................................................................................................. 43
Figure 4-11 : Direct Implementation of FIR filter on FPGA ...................................................................... 43
Figure 4-12 : Block diagram of CIC filter .................................................................................................. 44
Figure 4-13 : Implementing Sigma/Delta ADC on FPGA .......................................................................... 45
Figure 4-14 : Block diagram of the implemented Sigma/Delta ADC ......................................................... 45
Figure 4-15 : Coarse Time, Error1 and Error2 ............................................................................................ 47
Figure 4-16 : Generating slow and fast clocks at both edges of the error ................................................... 48
Figure 4-17 : The Block Diagram of the Fine Time Measurement ............................................................. 48
Figure 4-18 : First Design of Single-Slope ADC ........................................................................................ 49
Figure 4-19 : Chronogram of the standard single ramp ADC operation. .................................................... 50
Figure 4-20 : Second Design of Single-Slope ADC ................................................................................... 51
Figure 5-1 : Schematic Diagram of the Error Finder .................................................................................. 53
Figure 5-2 : Error Finder Simulation .......................................................................................................... 53
Figure 5-3 : Schematic Diagram of the TDC using Error Finder ............................................................... 55
Figure 5-4 : TDC Simulation ...................................................................................................................... 55
Figure 5-5 : Double Ring Oscillator with Stop and Go control .................................................................. 57
Figure 5-6 : Delay Locked Loop (DLL) ..................................................................................................... 58
Figure 5-7 : Schematic Diagram of Two Different Ring Oscillator ........................................................... 59
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