Table Of Content

TrimSize:170mmx244mm (cid:2) Lam ffirs.tex V3-12/01/2015 9:0-1080A.M. Pagei BOOLEAN CIRCUIT REWIRING (cid:2) (cid:2) (cid:2) TrimSize:170mmx244mm (cid:2) Lam ffirs.tex V3-12/01/2015 9:0-1080A.M. Pageii (cid:2) (cid:2) (cid:2) TrimSize:170mmx244mm (cid:2) Lam ffirs.tex V3-12/01/2015 9:0-1080A.M. Pageiii BOOLEAN CIRCUIT REWIRING: BRIDGING LOGICAL AND PHYSICAL DESIGNS Tak-KeiLam TheChineseUniversityofHongKong,HongKong,P.R.China Wai-ChungTang QueenMaryUniversityofLondon,UK XingWei (cid:2) (cid:2) Easy-LogicTechnologyLtd.HongKong,HongKong,P.R.China YiDiao Easy-LogicTechnologyLtd.HongKong,HongKong,P.R.China David Yu-LiangWu Easy-LogicTechnologyLtd.HongKong,HongKong,P.R.China (cid:2) TrimSize:170mmx244mm (cid:2) Lam ffirs.tex V3-12/01/2015 9:0-1080A.M. Pageiv Thiseditionfirstpublished2016 ©2016JohnWiley&SonsSingaporePteLtd Registeredoffice JohnWiley&SonsSingaporePteLtd,1FusionopolisWalk,#07-01SolarisSouthTower,Singapore138628. Fordetailsofourglobaleditorialoffices,forcustomerservicesandforinformationabouthowtoapplyfor permissiontoreusethecopyrightmaterialinthisbookpleaseseeourwebsiteatwww.wiley.com. TherightoftheauthortobeidentifiedastheauthorofthisworkhasbeenassertedinaccordancewiththeCopyright, DesignsandPatentsAct1988. Allrightsreserved.Nopartofthispublicationmaybereproduced,storedinaretrievalsystem,ortransmitted,inany formorbyanymeans,electronic,mechanical,photocopying,recordingorotherwise,exceptaspermittedbytheUK Copyright,DesignsandPatentsAct1988,withoutthepriorpermissionofthepublisher. Wileyalsopublishesitsbooksinavarietyofelectronicformats.Somecontentthatappearsinprintmaynotbe availableinelectronicbooks. Designationsusedbycompaniestodistinguishtheirproductsareoftenclaimedastrademarks.Allbrandnamesand productnamesusedinthisbookaretradenames,servicemarks,trademarksorregisteredtrademarksoftheir respectiveowners.Thepublisherisnotassociatedwithanyproductorvendormentionedinthisbook LimitofLiability/DisclaimerofWarranty:Whilethepublisherandauthorhaveusedtheirbesteffortsinpreparing thisbook,theymakenorepresentationsorwarrantieswithrespecttotheaccuracyorcompletenessofthecontentsof thisbookandspecificallydisclaimanyimpliedwarrantiesofmerchantabilityorfitnessforaparticularpurpose.Itis soldontheunderstandingthatthepublisherisnotengagedinrenderingprofessionalservicesandneitherthe publishernortheauthorshallbeliablefordamagesarisingherefrom.Ifprofessionaladviceorotherexpert assistanceisrequired,theservicesofacompetentprofessionalshouldbesought. (cid:2) (cid:2) LibraryofCongressCataloging-in-PublicationDataappliedfor. ISBN:9781118750117 AcataloguerecordforthisbookisavailablefromtheBritishLibrary. Setin10/12pt,TimesLTStdbySPiGlobal,Chennai,India. 1 2016 (cid:2) TrimSize:170mmx244mm (cid:2) Lam ftoc.tex V3-12/01/2015 9:0-1080A.M. Pagev Contents ListofFigures ix ListofTables xiii Preface xv Introduction xvii 1 Preliminaries 1 1.1 BooleanCircuits 1 (cid:2) 1.2 RedundancyandStuck-atFaults 4 (cid:2) 1.3 AutomaticTestPatternGeneration(ATPG) 6 1.4 Dominators 6 1.5 MandatoryAssignmentsandRecursiveLearning 7 1.6 GraphTheoryandBooleanCircuits 8 References 10 2 ConceptofLogicRewiring 11 2.1 WhatisRewiring? 11 2.2 ATPG-basedRewiringTechniques 12 2.2.1 Add-First 12 2.2.2 Delete-First 18 2.3 Non-ATPG-basedRewiringTechniques 24 2.3.1 Graph-basedAlternateWiring(GBAW) 24 2.3.2 SPFD 25 2.4 WhyareRewiringTechniquesImportant? 31 References 33 3 Add-FirstandNon-ATPG-BasedRewiringTechniques 37 3.1 RedundancyAdditionandRemoval(RAR) 37 3.1.1 RAMBO 37 3.1.2 REWIRE 38 3.1.3 RAMFIRE 41 3.1.4 ComparisonBetweenRAR-BasedRewiringTechniques 43 (cid:2) TrimSize:170mmx244mm (cid:2) Lam ftoc.tex V3-12/01/2015 9:0-1080A.M. Pagevi vi Contents 3.2 Node-BasedNetworkAdditionandRemoval(NAR) 43 3.2.1 NodeMerging 43 3.2.2 NodeAdditionandRemoval 48 3.3 OtherRewiringTechniques 51 3.3.1 SPFD-BasedRewiring 51 References 65 4 Delete-FirstRewiringTechniques 67 4.1 IRRA 69 4.1.1 DestinationofAlternativeWires 71 4.1.2 SourceofAlternativeWires 72 4.2 ECR 76 4.2.1 DestinationofAlternativeWires 80 4.2.2 SourceofAlternativeWires 85 4.2.3 OverviewoftheApproachofError-Cancellation-BasedRewiring 86 4.2.4 ComplexityAnalysisofECR 87 4.2.5 ComparisonBetweenECRandOtherResynthesisTechniques 90 4.2.6 ExperimentalResult 92 4.3 FECR 96 4.3.1 ErrorFlowGraphConstruction 97 4.3.2 DestinationNodeIdentification 98 4.3.3 SourceNodeIdentification 102 4.3.4 ECRisaSpecialCaseofFECR 104 (cid:2) (cid:2) 4.3.5 ComplexityAnalysisofFECR 105 4.3.6 ExperimentalResult 105 4.4 Cut-BasedErrorCancellationRewiring 107 4.4.1 Preliminaries 107 4.4.2 ErrorFrontier 109 4.4.3 Cut-BasedErrorCancellationRewiring 117 4.4.4 VerificationofAlternativeWires 121 4.4.5 ComplexityAnalysisofCECR 122 4.4.6 RelationshipBetweenECR,FECR,andCECR 122 4.4.7 ExtendingCECRforn-to-mRewiring 123 4.4.8 SpeedupforCECR 124 4.4.9 ExperimentalResults 125 References 129 5 Applications 133 5.1 AreaReduction 133 5.1.1 Preliminaries 134 5.1.2 OurMethodology(“Longtail”vs“Bumptail”Curves) 135 (cid:2) TrimSize:170mmx244mm (cid:2) Lam ftoc.tex V3-12/01/2015 9:0-1080A.M. Pagevii Contents vii 5.1.3 DetailsofourApproach 140 5.1.4 ExperimentalResults 143 5.2 PostplacementOptimization 145 5.2.1 Wire-Length-DrivenRewiring-BasedPostplacementOptimization 145 5.2.2 Timing-DrivenRewiring-BasedPostplacementOptimization 151 5.3 ECOTimingOptimization 158 5.3.1 Preliminaries 160 5.3.2 Nego-RoutOperation 161 5.3.3 Path-RestructuringOperation 164 5.3.4 ExperimentalResults 166 5.4 AreaReductioninFPGATechnologyMapping 167 5.4.1 IncrementalLogicResynthesis(ILR):Depth-OrientedMode 170 5.4.2 IncrementalLogicResynthesis(ILR):Area-OrientedMode 171 5.4.3 ExperimentalResults 173 5.4.4 Conclusion 183 5.5 FPGAPostlayoutRoutingOptimization 184 5.5.1 OptimizationbyAlternativeFunctions 185 5.5.2 OptimizationwithMapping-to-RoutingLogicRewirings 187 5.5.3 OptimizationbySPFD-BasedRewiring 198 5.6 LogicSynthesisforLowPowerUsingClockGatingandRewiring 199 5.6.1 MechanismofClockGating 199 5.6.2 Rewiring-BasedOptimization 203 References 207 (cid:2) (cid:2) 6 Summary 211 Index 213 (cid:2) TrimSize:170mmx244mm (cid:2) Lam ftoc.tex V3-12/01/2015 9:0-1080A.M. Pageviii (cid:2) (cid:2) (cid:2)

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Boolean circuit rewiring : bridging logical and physical designs PDF

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TrimSize:170mmx244mm (cid:2) Lam ffirs.tex V3-12/01/2015 9:0-1080A.M. Pagei BOOLEAN CIRCUIT REWIRING (cid:2) (cid:2) (cid:2) TrimSize:170mmx244mm (cid:2) Lam ffirs.tex V3-12/01/2015 9:0-1080A.M. Pageii (cid:2) (cid:2) (cid:2) TrimSize:170mmx244mm (cid:2) Lam ffirs.tex V3-12/01/2015 9:0-1080A.M. Pageiii BOOLEAN CIRCUIT REWIRING: BRIDGING LOGICAL AND PHYSICAL DESIGNS Tak-KeiLam TheChineseUniversityofHongKong,HongKong,P.R.China Wai-ChungTang QueenMaryUniversityofLondon,UK XingWei (cid:2) (cid:2) Easy-LogicTechnologyLtd.HongKong,HongKong,P.R.China YiDiao Easy-LogicTechnologyLtd.HongKong,HongKong,P.R.China David Yu-LiangWu Easy-LogicTechnologyLtd.HongKong,HongKong,P.R.China (cid:2) TrimSize:170mmx244mm (cid:2) Lam ffirs.tex V3-12/01/2015 9:0-1080A.M. Pageiv Thiseditionfirstpublished2016 ©2016JohnWiley&SonsSingaporePteLtd Registeredoffice JohnWiley&SonsSingaporePteLtd,1FusionopolisWalk,#07-01SolarisSouthTower,Singapore138628. Fordetailsofourglobaleditorialoffices,forcustomerservicesandforinformationabouthowtoapplyfor permissiontoreusethecopyrightmaterialinthisbookpleaseseeourwebsiteatwww.wiley.com. TherightoftheauthortobeidentifiedastheauthorofthisworkhasbeenassertedinaccordancewiththeCopyright, DesignsandPatentsAct1988. Allrightsreserved.Nopartofthispublicationmaybereproduced,storedinaretrievalsystem,ortransmitted,inany formorbyanymeans,electronic,mechanical,photocopying,recordingorotherwise,exceptaspermittedbytheUK Copyright,DesignsandPatentsAct1988,withoutthepriorpermissionofthepublisher. Wileyalsopublishesitsbooksinavarietyofelectronicformats.Somecontentthatappearsinprintmaynotbe availableinelectronicbooks. Designationsusedbycompaniestodistinguishtheirproductsareoftenclaimedastrademarks.Allbrandnamesand productnamesusedinthisbookaretradenames,servicemarks,trademarksorregisteredtrademarksoftheir respectiveowners.Thepublisherisnotassociatedwithanyproductorvendormentionedinthisbook LimitofLiability/DisclaimerofWarranty:Whilethepublisherandauthorhaveusedtheirbesteffortsinpreparing thisbook,theymakenorepresentationsorwarrantieswithrespecttotheaccuracyorcompletenessofthecontentsof thisbookandspecificallydisclaimanyimpliedwarrantiesofmerchantabilityorfitnessforaparticularpurpose.Itis soldontheunderstandingthatthepublisherisnotengagedinrenderingprofessionalservicesandneitherthe publishernortheauthorshallbeliablefordamagesarisingherefrom.Ifprofessionaladviceorotherexpert assistanceisrequired,theservicesofacompetentprofessionalshouldbesought. (cid:2) (cid:2) LibraryofCongressCataloging-in-PublicationDataappliedfor. ISBN:9781118750117 AcataloguerecordforthisbookisavailablefromtheBritishLibrary. Setin10/12pt,TimesLTStdbySPiGlobal,Chennai,India. 1 2016 (cid:2) TrimSize:170mmx244mm (cid:2) Lam ftoc.tex V3-12/01/2015 9:0-1080A.M. Pagev Contents ListofFigures ix ListofTables xiii Preface xv Introduction xvii 1 Preliminaries 1 1.1 BooleanCircuits 1 (cid:2) 1.2 RedundancyandStuck-atFaults 4 (cid:2) 1.3 AutomaticTestPatternGeneration(ATPG) 6 1.4 Dominators 6 1.5 MandatoryAssignmentsandRecursiveLearning 7 1.6 GraphTheoryandBooleanCircuits 8 References 10 2 ConceptofLogicRewiring 11 2.1 WhatisRewiring? 11 2.2 ATPG-basedRewiringTechniques 12 2.2.1 Add-First 12 2.2.2 Delete-First 18 2.3 Non-ATPG-basedRewiringTechniques 24 2.3.1 Graph-basedAlternateWiring(GBAW) 24 2.3.2 SPFD 25 2.4 WhyareRewiringTechniquesImportant? 31 References 33 3 Add-FirstandNon-ATPG-BasedRewiringTechniques 37 3.1 RedundancyAdditionandRemoval(RAR) 37 3.1.1 RAMBO 37 3.1.2 REWIRE 38 3.1.3 RAMFIRE 41 3.1.4 ComparisonBetweenRAR-BasedRewiringTechniques 43 (cid:2) TrimSize:170mmx244mm (cid:2) Lam ftoc.tex V3-12/01/2015 9:0-1080A.M. Pagevi vi Contents 3.2 Node-BasedNetworkAdditionandRemoval(NAR) 43 3.2.1 NodeMerging 43 3.2.2 NodeAdditionandRemoval 48 3.3 OtherRewiringTechniques 51 3.3.1 SPFD-BasedRewiring 51 References 65 4 Delete-FirstRewiringTechniques 67 4.1 IRRA 69 4.1.1 DestinationofAlternativeWires 71 4.1.2 SourceofAlternativeWires 72 4.2 ECR 76 4.2.1 DestinationofAlternativeWires 80 4.2.2 SourceofAlternativeWires 85 4.2.3 OverviewoftheApproachofError-Cancellation-BasedRewiring 86 4.2.4 ComplexityAnalysisofECR 87 4.2.5 ComparisonBetweenECRandOtherResynthesisTechniques 90 4.2.6 ExperimentalResult 92 4.3 FECR 96 4.3.1 ErrorFlowGraphConstruction 97 4.3.2 DestinationNodeIdentification 98 4.3.3 SourceNodeIdentification 102 4.3.4 ECRisaSpecialCaseofFECR 104 (cid:2) (cid:2) 4.3.5 ComplexityAnalysisofFECR 105 4.3.6 ExperimentalResult 105 4.4 Cut-BasedErrorCancellationRewiring 107 4.4.1 Preliminaries 107 4.4.2 ErrorFrontier 109 4.4.3 Cut-BasedErrorCancellationRewiring 117 4.4.4 VerificationofAlternativeWires 121 4.4.5 ComplexityAnalysisofCECR 122 4.4.6 RelationshipBetweenECR,FECR,andCECR 122 4.4.7 ExtendingCECRforn-to-mRewiring 123 4.4.8 SpeedupforCECR 124 4.4.9 ExperimentalResults 125 References 129 5 Applications 133 5.1 AreaReduction 133 5.1.1 Preliminaries 134 5.1.2 OurMethodology(“Longtail”vs“Bumptail”Curves) 135 (cid:2) TrimSize:170mmx244mm (cid:2) Lam ftoc.tex V3-12/01/2015 9:0-1080A.M. Pagevii Contents vii 5.1.3 DetailsofourApproach 140 5.1.4 ExperimentalResults 143 5.2 PostplacementOptimization 145 5.2.1 Wire-Length-DrivenRewiring-BasedPostplacementOptimization 145 5.2.2 Timing-DrivenRewiring-BasedPostplacementOptimization 151 5.3 ECOTimingOptimization 158 5.3.1 Preliminaries 160 5.3.2 Nego-RoutOperation 161 5.3.3 Path-RestructuringOperation 164 5.3.4 ExperimentalResults 166 5.4 AreaReductioninFPGATechnologyMapping 167 5.4.1 IncrementalLogicResynthesis(ILR):Depth-OrientedMode 170 5.4.2 IncrementalLogicResynthesis(ILR):Area-OrientedMode 171 5.4.3 ExperimentalResults 173 5.4.4 Conclusion 183 5.5 FPGAPostlayoutRoutingOptimization 184 5.5.1 OptimizationbyAlternativeFunctions 185 5.5.2 OptimizationwithMapping-to-RoutingLogicRewirings 187 5.5.3 OptimizationbySPFD-BasedRewiring 198 5.6 LogicSynthesisforLowPowerUsingClockGatingandRewiring 199 5.6.1 MechanismofClockGating 199 5.6.2 Rewiring-BasedOptimization 203 References 207 (cid:2) (cid:2) 6 Summary 211 Index 213 (cid:2) TrimSize:170mmx244mm (cid:2) Lam ftoc.tex V3-12/01/2015 9:0-1080A.M. Pageviii (cid:2) (cid:2) (cid:2)

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