Audio Codec with Embedded miniDSP, Stereo Class-D Speaker Amplifier

191 Pages·2016·1.86 MB·English

TSC2117
www.ti.com SLAS550B–APRIL2009–REVISEDJUNE2012
Low-Power Audio Codec with Embedded miniDSP,
Stereo Class-D Speaker Amplifier, and
Smart Four-Wire Touch-Screen Controller
CheckforSamples:TSC2117
1 INTRODUCTION
AuxiliaryMeasurements
1.1 Features
• ProgrammableDRCforDigital Playback
• Low-Power13-mWStereo48-kHzPlayback
1234 • Sine-WaveGenerator forBeepGeneratorfor
• Stereo AudioDACandMonauralADCSupport
Touch-PadPressAcknowledgement
8-kHzto192-kHzSampleRates
• IntegratedPLLUsedforProgrammableDigital
• Instruction-ProgrammableminiDSPAvailable
AudioProcessor
forRecordandPlaybackPaths
• SPI,I2C,andI2SSerial Interfaces
• BassBoost/Treble/EQWithuptoFiveBiquads
• SPI ,I2CHaveRegisterAuto-Increment
forRecordanduptoSixBiquadsforPlayback
• FullPower-DownControl
• Stereo 1.29-WClass-DBTL8-ΩSpeakerDriver
• PowerSupplies:
WithDirectBatteryConnection
– Analog: 2.7V–3.6V
• SmartFour-WireTouch-ScreenController With
AutonomousTiming – Digital Core:1.65V–1.95V
• Programmable-GainAmplifiers – Digital I/O: 1.1V–3.6V
• MicrophoneBias – Class-D:2.7V–5.5V(SLVDDandSRVDD ≥
AVDD)
• Hardware-ImplementedAGCUsedWith
MicrophoneInputforAudioADCPath • 7-mm× 7-mm 48-QFNPackage
• DigitalMicrophoneInterface
• DigitalMixingCapability 1.2 Applications
• PinControlor RegisterControl forDigital- • PortableGamingDevices
PlaybackVolume-Control Settings
• MobileInternet Devices
• Programmable12-BitSARADC
• AdaptiveFilteringApplications
• Built-InCapabilityfor Temperature,Battery,or
1.3 Description
The TSC2117 is a low-power, highly integrated, high-performance codec and touch-screen controller which
featuresstereoclass-D speakeramplifiers,astereoaudioDAC,monoaudioADC,andaSARADC.
The TSC2117 supports 16-bit stereo playback and monaural record functionality. The device integrates several
analogfeatures,suchasamicrophoneinterface,headphonedrivers,andspeakerdrivers.TheTSC2117 hastwo
fully programmable miniDSPs for digital audio processing. The digital audio data format is programmable to work
with popular audio standard protocols (I2S, left/right-justified) in master, slave, DSP, and TDM modes. Bass
boost, treble, or EQ are supported by the preprogrammed modes of the programmable digital signal-processing
block. An on-chip PLL provides the high-speed clock needed by the digital signal-processing block. The volume
levelcanbecontrolledbyeitherapincontrolorbyregistercontrol.
The TSC2117 has a 12-bit SAR ADC converter that supports a four-wire resistive touch-screen complete with
drivers. All functions can be controlled by an I2C or SPI interface. A programmable beep generator is included.
An on-chip processor is used in the touch-screen mode and provides extensive features specifically designed to
reduce the host-processor and interface-bus overhead. The TSC2117 has three dedicated analog inputs for
system voltage measurements, with an on-chip temperature sensor that can be read by the SAR ADC, and is
availableina7-mm×7-mm48-pinQFNpackage.
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PurePathisatrademarkofTexasInstruments.
2
MATLABisatrademarkofTheMathWorks,Inc.
3
Allothertrademarksarethepropertyoftheirrespectiveowners.
4
PRODUCTIONDATAinformationiscurrentasofpublicationdate.Productsconformto Copyright©2009–2012,TexasInstrumentsIncorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processingdoesnotnecessarilyincludetestingofallparameters.
TSC2117
SLAS550B–APRIL2009–REVISEDJUNE2012 www.ti.com
SLVDD SRVDD SLVSS SRVSS HVDD HVSS AVDD AVSS
MICBIAS 2 V/2.5 V/AVDD P1/R33–R34 De-Pop
P0/R116 and Audio Output Stage
VOL/ Soft- Power Management
MICDET 7-BitADC Start
Left and Right Volume-
Control Register RC CLK
P0/R65–R66 GPIO1
GPIO2
Class-D Speaker AnalogAttenuation
Driver 0 dB to–78 dB and Mute GPIO GPI1
(0.5-dB Steps / Nonlinear) GPI2
SPLP P1/R42 P1/R38 MIX_L GPI3
SPLN
SPRP P1/R32 6 dB to 24 PdB1/ R (64-3dB Steps) P1/R39 MIX_R NaI2rCoet eoc:or AnSltlPr ofIu.ll naItcb itlsieo nnvosiat I2C SSCDLA
SPRN recommended to
P1/R30 use both I2C and SS
ClassA/B AnalogAttenuation SPI simultaneously. SCLK
Headphone/Lineout 0 dB to–78 dB and Mute SPI
Driver (0.5-dB Steps / Nonlinear) MOSI
P1/R40 P1/R36 MIX_L MISO
HPL
P1/R31 0 dB to 9 dB (1-dB Steps) Note: Normally,
MCLK is PLLinput;
P1/R44 P1/R41 P1/R37 MIX_R however, BCLK,
HPR GPIO1, etc., can
also be PLLinput.
MIX_R
MIX_L PLL MCLK
MIC2_LINE_L
S DAC_L D-S S S
DAC
AUX1_MIC3_LINE_R Digital Vol Prog
P1/R35 24 dB to DSP P0/R63
Mute Engine Digital
Audio
S DAC_R D-S S S Processing
DAC and
P0/R64
Serial
Digital P0/R71 Digital Beep Interface SDOUT
P0/R72
Vol Ctl Generator WCLK
2 to–61 dB
P1/R47 (1-dB Steps) SDIN
MIC2_LINE_L 0 to 59.5 dB
MIC (0.5-dB steps) MonoADC P0/R82–R83 BCLK
AUX2_MIC1 S
D-S Digital Vol Prog
AUX1_MIC3_LINE_R ADC –12..20 dB DSP
P1/R48 Step = 0.5 dB Engine
Selectable P0/R86–R93
Gain/Input
Impedance AGC
AUX2_MIC1 S Clock Data Note: Digital Mic
Clock and Data
Digtal Mic
VCOM Interface routed to GPIO1
InPp1u/Rt C50M SGealienc/Itnapbulet P1/R49 aPn0d/R G5P1–IOR25 2pins. RESET
Impedance Divider MCLK
TSVDD
RC CLK
P3/R4–R5
P3/R15–R16
XP
Touch- SAR_Mode
YP
Panel
XN P3/R17
Drivers
YN P3/R2–R3 Touch-
AUX1 SAR Screen
Processing
AUX2 ADC
Control
VBAT ÷5 Reference OSC Interface
FIFO
(InVtRerEnFal) RC CLK P3/R13
P3/R6
TSVDD TSVSS VREF DVDD DVSS IOVDD IOVSS
B0205-04
Figure1-1. Functional BlockDiagram
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all
integrated circuits be handled with appropriate precautions. Failure to observe proper
handlingandinstallationprocedurescancausedamage.
ESD damage can range from subtle performance degradation to complete device failure.
Precision integrated circuits may be more susceptible to damage because very small
parametricchangescouldcausethedevicenottomeet itspublishedspecifications.
NOTE
Thisdatamanualis designedusingPDFdocument-viewingfeatures thatallowquick access
to information. For example, performing a global search on, e.g., "page 0/register 15"
produces allreferences to thispage andregister inalist.Thismakes is easy to traverse the
listandfindallinformationrelatedtoapageandregister.Notethatthesearchstringmustbe
of the indicated format. Also, this document includes document hyperlinks to allow the user
to quickly find a document reference. To come back to the original page, click the green left
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2 PACKAGE AND SIGNAL DESCRIPTIONS
2.1 Package/Ordering Information
OPERATING
PACKAGE TRANSPORTMEDIA,
PRODUCT PACKAGE TEMPERATURE ORDERINGNUMBER
DESIGNATOR QUANTITY
RANGE
TSC2117IRGZT Tapeandreel,250
TSC2117 QFN-48 RGZ –40°Cto85°C
TSC2117IRGZR Tapeandreel,2500
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2.2 Device Information
RGZ Package
(Top View)
T S D
E S D P S D N
ES PI1 PI2 PI3 PR VS VD PL PR RV RV PR
R G G G H H H H S S S S
8 7 6 5 4 3 2 1 0 9 8 7
4 4 4 4 4 4 4 4 4 3 3 3
MISO 1 36 SPLP
MOSI 2 35 SLVDD
SS 3 34 SLVSS
SCLK 4 33 SPLN
GPIO1 5 32 TSVDD
GPIO2 6 31 XP
TSC2117
IOVSS 7 30 YP
IOVDD 8 29 DVSS
DVDD 9 28 XN
SDOUT 10 27 YN
SDIN 11 26 TSVSS
WCLK 12 25 VREF
3 4 5 6 7 8 9 0 1 2 3 4
1 1 1 1 1 1 1 2 2 2 2 2
K K A L T S C 1 2 S D T
BCL MCL SD SC CDE CBIA MI AUX AUX AVS AVD VBA
MI MI
L/
O
V
P0023-17
Table2-1. TERMINALFUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
AUX1(primaryaux.inputtoSARADC),alsoroutedtoaudioADCinputmixerandaudioDAC
AUX1 20 I
outputmixer
AUX2 21 I AUX2(secondaryaux.inputtoSARADC),alsoroutedtoaudioADCinputmixer
AVDD 23 – Analogpowersupply
AVSS 22 – Analogground
BCLK 13 I/O Audioserialclock
DVDD 9 – Digitalpower–digitalcore
DVSS 29 – Digitalground(internallyconnectedtoHVSS)
GPI1 47 I General-purposeinputandmultifunctionpin
GPI2 46 I General-purposeinputandmultifunctionpin
GPI3 45 I General-purposeinputandmultifunctionpin
GPIO1 5 I/O General-purposeinput/outputpinandmultifunctionpin
GPIO2 6 I/O General-purposeinput/outputpinandmultifunctionpin
HPL 41 O Left-channelheadphonedriveroutput
HPR 44 O Right-channelheadphonedriveroutput
HVDD 42 – HeadphonedriverandPLLpower
HVSS 43 – DriverandPLLground(internallyconnectedtoDVSS)
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Table2-1.TERMINALFUNCTIONS(continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
IOVDD 8 – Digitalinterfacepower
IOVSS 7 – Digitalinterfaceground
MCLK 14 I Externalmasterclock
MIC 19 I Microphoneinput(routedtoaudioADCinputmixerandaudioDACoutputmixer)
MICBIAS 18 O Microphonebiasvoltage
MISO 1 O DataoutputfromSPI(Hi-Zcapable)
MOSI 2 I DatainputtoSPI
RESET 48 I Resetforlogicandallinternalregisters–active-low
SCL 16 I/O I2Ccontrolbusclockinput
SCLK 4 I ExternalclocktoSPI
SDA 15 I/O I2Ccontrol-busdataI/O
SDIN 11 I Playbackaudioserial-datainput
SDOUT 10 O Recordaudioserial-dataoutput(hi-Zcapable)
SLVDD 35 – Left-channelclass-Dspeaker-amplifierpowersupply
SLVSS 34 – Left-channelclass-Dspeaker-amplifierpower-supplyground
SPLN 33 O Left-channelspeaker-driverinvertingoutput
SPLP 36 O Left-channelspeaker-drivernoninvertingoutput
SPRN 37 O Right-channelspeaker-driverinvertingoutput
SPRP 40 O Right-channelspeaker-drivernoninvertingoutput
SRVDD 38 – Right-channelclass-Dspeaker-amplifierpowersupply
SRVSS 39 – Right-channelclass-Dspeaker-amplifierpower-supplyground
SS 3 I SPIchipselect–active-low
TSVDD 32 – Touch-screencontrollerpower(usedfortouch-screenpaneldriver)
TSVSS 26 – Touch-screendriverground
VBAT 24 I Battery-monitorinputtoSARADC
VOL/MICDET 17 I Playbackdigitalvolumecontrolormicrophone-detectionfunctionality
VREF 25 I/O VoltagereferenceinputforSARADC
WCLK 12 I/O Audioserial-buschannelclock
XN 28 I/O Touch-screenX–positionalinputanddriver
XP 31 I/O Touch-screenX+positionalinputanddriver
YN 27 I/O Touch-screenY–positionalinputanddriver
YP 30 I/O Touch-screenY+positionalinputanddriver
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3 ELECTRICAL SPECIFICATIONS
3.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)
VALUE UNIT
AVDDtoAVSS –0.3to3.9 V
DVDDtoDVSS –0.3to2.5 V
HVDDtoHVSS –0.3to3.9 V
SLVDDtoSLVSS –0.3to6 V
SRVDDtoSRVSS –0.3to6 V
IOVDDtoIOVSS –0.3to3.9 V
TSVDDtoTSVSS –0.3to3.9 V
VREFtoAVSS AVSS–0.3toAVDD V
Digitalinputvoltage IOVSS–0.3toIOVDD+0.3 V
Analoginputvoltage AVSS–0.3toAVDD+0.3 V
VBAT –0.3to6 V
Operatingtemperaturerange –40to85 °C
Storagetemperaturerange –55to150 °C
Junctiontemperature(T Max) 105 °C
J
Powerdissipation (T Max–T )/R W
J A θJA
QFNpackage
R Thermalimpedance(withthermalpadsolderedtoboard) 27 °C/W
θJA
Leadtemperature Infrared(15s) 300 °C
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating
Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
Table3-1.System ThermalCharacteristics(1)
PowerRatingat25°C DeratingFactor PowerRatingat70°C PowerRatingat85°C
3W 37.04mW/°C 1.3W 0.74W
(1) Thisdatawastakenusing2-oz.(0.071-mmthick)traceandcopperpadthatissolderedtoaJEDEChigh-K,standard4-layer3-in.×3
in.(7.62-cm×7.62-cm)PCB.
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3.2 Recommended Operating Conditions
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
AVDD(1) ReferencedtoAVSS(2) 2.7 3.3 3.6
DVDD ReferencedtoDVSS(2) 1.65 1.8 1.95
HVDD ReferencedtoHVSS(2) 2.7 3.3 3.6
SLVDD(1) Power-supplyvoltagerange ReferencedtoSLVSS(2) 2.7 5.5 V
SRVDD(1) ReferencedtoSRVSS(2) 2.7 5.5
TSVDD ReferencedtoTSVSS(2) 2.7 3.3 3.6
IOVDD ReferencedtoIOVSS(2) 1.1 3.3 3.6
VREF Externalvoltagereference ReferencedtoAVSS(2) 0 3.3 AVDD V
Resistanceappliedacrossclass-Doutputpins
Speakerimpedance 8 Ω
(BTL)
Headphoneimpedance ACcoupledtoR 16 Ω
L
Analogaudiofull-scaleinput
V AVDD=3.3V,single-ended 0.707 V
I voltage RMS
Stereolineoutputload
ACcoupledtoR 10 kΩ
impedance L
MCLK(3) Masterclockfrequency IOVDD=3.3V 50 MHz
SCLKfrequency IOVDD=3.3V 30 MHz
SCLK
SCLKdutycycle 40% 50% 60%
SCL SCLclockfrequency 400 kHz
T Operatingfree-airtemperature –40 85 °C
A
(1) Tominimizebattery-currentleakage,theSLVDDandSRVDDvoltagelevelsshouldnotbebelowtheAVDDvoltagelevel.
(2) Allgroundsonboardaretiedtogether,sotheyshouldnotdifferinvoltagebymorethan0.2Vmaximumforanycombinationofground
signals.Byuseofawidetraceorgroundplane,ensurealow-impedanceconnectionbetweenHVSSandDVSS.
(3) Themaximuminputfrequencyshouldbe50MHzforanydigitalpinusedasageneral-purposeclock.
3.3 Electrical Characteristics
At25°C,AVDD,HVDD,IOVDD,TSVDD,=3.3V,SLVDD,SRVDD=3.6V,DVDD=1.8V,VREF=3.3V,f (audio)=
S
48kHz,CODEC_CLKIN=256×f ,PLL=Off,SARinputisAUX1,VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
SARCONVERTER
AuxilaryAnalogInput
Inputvoltagerange 0 VREF V
Inputimpedance(1) AUX1,AUX2,VBATinputselectedasinputbytouch 1/(f×C) kΩ
Inputcapacitance screen 25 pF
Inputleakagecurrent 1 μA
InputvoltagerangeforVBAT Battery-measurementmode 0 6 V
(1) SARinputimpedanceisdependentonthesamplingfrequency,wherethesamplingcapacitorisC=25pF.
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ElectricalCharacteristics(continued)
At25°C,AVDD,HVDD,IOVDD,TSVDD,=3.3V,SLVDD,SRVDD=3.6V,DVDD=1.8V,VREF=3.3V,f (audio)=
S
48kHz,CODEC_CLKIN=256×f ,PLL=Off,SARinputisAUX1,VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
Touch-ScreenSARADC
Resolution Programmable:8-bit,10-bit,12-bit 8 12 Bits
Nomissingcodes 12-bitresolution 11 Bits
INL Integralnonlinearity 12-bitresolution,conversionclock=2MHz ±7 LSB
Offseterror 12-bitresolution,conversionclock=2MHz ±7 LSB
Gainerror 12-bitresolution,conversionclock=2MHz ±7 LSB
12-bitresolution,conversionclock=2MHz,
Noise 0.8 LSB
AUX2=1Vdc
ConversionRate
Normalconversionoperation 12bits,internalconversionclock=2MHz 119 kHz
High-speedconversion 8bits,internalconversionclock=6MHz(Conversion
250 kHz
operation accuracyisreduced.)
VoltageReference—VREF
InternalVREF 1.25 2.5
Voltagerange V
ExternalVREF 1.25 AVDD
Measuredwith1-μFcapacitortoanalogground.
InternalVREFoutputvoltage InternalVREFselectedas1.25V(page3/register6, 1.23 V
bitD6=0)
INTERNALOSCILLATOR—RC_CLK
OscillatorfrequencyforSAR 8.2 MHz
VOLUMECONTROLPIN(ADC);VOL/MICDETpinenabled
VOL/MICDETpinconfiguredasvolumecontrol(page
0.5×
Inputvoltagerange 0/register116,bitD7=1andpage0/register67,bit 0 V
AVDD
D7=0)
Inputcapacitance 2 pF
Volumecontrolsteps 128 Steps
AUDIOADC
MicrophoneInputtoADC,984-HzSine-WaveInput,f =48kHz,AGC=OFF
S
MICwithR1=20kΩ(page1/register48andregister
Inputsignallevel(0-dB) 0.707 V
49,bitsD7–D6) RMS
f =48kHz,0-dBPGAgain,MICinputac-shortedto
S
SNR Signal-to-noiseratio ground;measuredasidle-channelnoise, 80 90 dB
A-weighted(1) (2)
f =48kHz,0-dBPGAgain,MICinput1kHzat–60-
S
Dynamicrange dBFSinputapplied,referencedto0.707-Vrmsinput, 91 dB
A-weighted(1)(2)
Totalharmonicdistortion+ f =48kHz,0-dBPGAgain,MICinput1kHzat–2
THD+N S –83 –70 dB
noise dBFSinputapplied,referencedto0.707Vrmsinput
f =48kHz,0-dBPGAgain,MICinput1kHzat–2
THD Totalharmonicdistortion S –90 dB
dBFSinputapplied,referencedto0.707Vrmsinput
Inputcapacitance MICinput 2 pF
(1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measuredA-weightedovera
20-Hzto20-kHzbandwidthusinganaudioanalyzer.
(2) Allperformancemeasurementsdonewith20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay
resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter
removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
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ElectricalCharacteristics(continued)
At25°C,AVDD,HVDD,IOVDD,TSVDD,=3.3V,SLVDD,SRVDD=3.6V,DVDD=1.8V,VREF=3.3V,f (audio)=
S
48kHz,CODEC_CLKIN=256×f ,PLL=Off,SARinputisAUX1,VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
MicrophoneBias
Page1/register46,bitsD1–D0=10 2.25 2.5 2.75
Voltageoutput V
Page1/register46,bitsD1–D0=01 2
At4-mAloadcurrent,page1/register46,bitsD1–D0
5
=10(MICBIAS=2.5V)
Voltageregulation mV
At4-mAloadcurrent,page1/register46,bitsD1–D0
7
=01(MICBIAS=2V)
AudioADCDigitalDecimationFilterCharacteristics
SeeSection5.5.4.4foraudioADCdecimationfiltercharacteristics.
DACHEADPHONEOUTPUT,AC-coupledload=16Ω(single-ended),
drivergain=0dB,parasiticcapacitance=30pF
Full-scaleoutputvoltage(0
Outputcommon-modesetting=1.65V 0.707 Vrms
dB)
SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted(1) (2) 80 95 dB
THD Totalharmonicdistortion 0-dBFSinput –85 –65 dB
Totalharmonicdistortion+
THD+N 0-dBFSinput –82 –60 dB
noise
Muteattenuation 87 dB
PSRR Power-supplyrejectionratio(3) RippleonHVDD(3.3V)=200mVp-pat1kHz 62 dB
R =32Ω,THD+N≤–60dB 20
L
P Maximumoutputpower mW
O
R =16Ω,THD+N≤–60dB 60
L
DACLINEOUT(HPDriverinLineoutMode)
SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted 95 dB
THD Totalharmonicdistortion 0-dBFSinput,0-dBgain –86 dB
Totalharmonicdistortion+
THD+N 0-dBFSinput,0-dBgain –82 dB
noise
DACDigitalInterpolationFilterCharacteristics
SeeSection5.6.1.4forDACinterpolationfiltercharacteristics.
DACOUTPUTtoCLASS-DSPEAKEROUTPUT;Load=8Ω(differential),50pF
SLVDD=SRVDD=3.6V,BTLmeasurement,DAC
input=0dBFS,DACVCM(page1/register31,bits
2.2
D4–D3)=1.65V,class-Dgain=6dB,
Outputvoltage THD≤–16.5dB Vrms
SLVDD=SRVDD=3.6V,BTLmeasurement,DAC
input=–2dBFS,DACVCM(page1/register31,bits 2.1
D4–D3)=1.65V,class-Dgain=6dB,THD≤–20dB
SLVDD=SRVDD=3.6V,BTLmeasurement,DAC
Output,common-mode input=mute,DACVCM(page1/register31,bits 1.65 V
D4–D3)=1.65V,class-Dgain=6dB
SLVDD=SRVDD=3.6V,BTLmeasurement,class-
Dgain=6dB,measuredasidle-channelnoise,A-
SNR Signal-to-noiseratio 87 dB
weighted(withrespecttofull-scaleoutputvalueof2.2
Vrms)(1) (2)
(1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measuredA-weightedovera
20-Hzto20-kHzbandwidthusinganaudioanalyzer.
(2) Allperformancemeasurementsdonewith20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay
resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter
removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
éVSIG ù
PSRR=20log ê Suppú
(3) DACtoheadphone-outPSRRmeasurementiscalculatedas 10êëVDACOUT úû
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ElectricalCharacteristics(continued)
At25°C,AVDD,HVDD,IOVDD,TSVDD,=3.3V,SLVDD,SRVDD=3.6V,DVDD=1.8V,VREF=3.3V,f (audio)=
S
48kHz,CODEC_CLKIN=256×f ,PLL=Off,SARinputisAUX1,VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DACOUTPUTtoCLASS-DSPEAKEROUTPUT;Load=8Ω(differential),50pF(continued)
SLVDD=SRVDD=3.6V,BTLmeasurement,DAC
THD Totalharmonicdistortion input=–6dBFS,DACVCM(page1/register31,bits –72 dB
D4–D3)=1.65V,class-Dgain=6dB
SLVDD=SRVDD=3.6V,BTLmeasurement,DAC
Totalharmonicdistortion+
THD+N input=–6dBFS,DACVCM(page1/register31,bits –71 dB
noise
D4–D3)=1.65V,class-Dgain=6dB
PSRR Power-supplyrejectionratio(1) SLVDD=SRVDD=3.6V,BTLmeasurement,ripple 57 dB
onSLVDD/SRVDD=200mVp-pat1kHz
Muteattenuation 110 dB
SLVDD=SRVDD=3.6V,BTLmeasurement,DAC
VCM(page1/register31,bitsD4–D3)=1.65V, 540
class-Dgain=18dB,THD=10%
mW
SLVDD=SRVDD=4.3V,BTLmeasurement,DAC
P Maximumoutputpower VCM(page1/register31,bitsD4–D3)=1.65V, 790
O
class-Dgain=18dB,THD=10%
SLVDD=SRVDD=5.5V,BTLmeasurement,DAC
VCM(page1/register31,bitsD4–D3)=1.65V, 1.29 W
class-Dgain=18dB,THD=10%
Output-stageleakagecurrent SLVDD=SRVDD=4.3V,deviceispowereddown
80 nA
fordirectbatteryconnection (power-up-resetcondition)
ADCandDACPOWERCONSUMPTION
ForADCandDACpowerconsumptionbasedperselectedprocessingblock,seeSection5.4
DIGITALINPUT/OUTPUT
Logic
CMOS
family
0.7×
I =5μA,IOVDD≥1.6V
V IH IOVDD V
IH
I =5μA,IOVDD<1.6V IOVDD
IH
0.3×
I =5μA,IOVDD≥1.6V –0.3
V IL IOVDD V
IL Logiclevel
I =5μA,IOVDD<1.6V 0
IL
0.8×
V I =2TTLloads V
OH OH IOVDD
0.1×
V I =2TTLloads V
OL OL IOVDD
Capacitiveload 10 pF
(cid:3)VSIGSupp(cid:4)
PSRR(cid:1)20log10 V
(1) DACtospeaker-outPSRRmeasurementiscalculatedas SPK1(cid:2)2 .
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