Table Of Content

Artificial Intelligence Applications and Reconfigurable Architectures Scrivener Publishing 100 Cummings Center, Suite 541J Beverly, MA 01915-6106 Publishers at Scrivener Martin Scrivener ([email protected]) Phillip Carmical ([email protected]) Artificial Intelligence Applications and Reconfigurable Architectures Edited by Anuradha D. Thakare Department of Computer Engineering, Pimpri Chinchwad College of Engineering, Pune, India and Sheetal Umesh Bhandari Department of Electronics and Telecommunication Engineering, Pimpri Chinchwad College of Engineering, Pune, India This edition first published 2023 by John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, USA and Scrivener Publishing LLC, 100 Cummings Center, Suite 541J, Beverly, MA 01915, USA © 2023 Scrivener Publishing LLC For more information about Scrivener publications please visit www.scrivenerpublishing.com. All rights reserved. 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Library of Congress Cataloging-in-Publication Data ISBN 978-1-119-85729-7 Cover image: Pixabay.Com Cover design by Russell Richardson Set in size of 11pt and Minion Pro by Manila Typesetting Company, Makati, Philippines Printed in the USA 10 9 8 7 6 5 4 3 2 1 Contents Preface xiii 1 Strategic Infrastructural Developments to Reinforce Reconfigurable Computing for Indigenous AI Applications 1 Deepti Khurge 1.1 Introduction 2 1.2 Infrastructural Requirements for AI 2 1.3 Categories in AI Hardware 4 1.3.1 Comparing Hardware for Artificial Intelligence 8 1.4 Hardware AI Accelerators to Support RC 9 1.4.1 Computing Support for AI Application: Reconfigurable Computing to Foster the Adaptation 9 1.4.2 Reconfiguration Computing Model 10 1.4.3 Reconfigurable Computing Model as an Accelerator 11 1.5 Architecture and Accelerator for AI-Based Applications 15 1.5.1 Advantages of Reconfigurable Computing Accelerators 20 1.5.2 Disadvantages of Reconfigurable Computing Accelerators 21 1.6 Conclusion 22 References 22 2 Review of Artificial Intelligence Applications and Architectures 25 Rashmi Mahajan, Dipti Sakhare and Rohini Gadgil 2.1 Introduction 25 2.2 Technological Platforms for AI Implementation—Graphics Processing Unit 27 2.3 Technological Platforms for AI Implementation—Field Programmable Gate Array (FPGA) 28 v vi Contents 2.3.1 Xilinx Zynq 28 2.3.2 Stratix 10 NX Architecture 29 2.4 Design Implementation Aspects 30 2.5 Conclusion 32 References 32 3 An Organized Literature Review on Various Cubic Root Algorithmic Practices for Developing Efficient VLSI Computing System—Understanding Complexity 35 Siba Kumar Panda, Konasagar Achyut, Swati K. Kulkarni, Akshata A. Raut and Aayush Nayak 3.1 Introduction 36 3.2 Motivation 37 3.3 Numerous Cubic Root Methods for Emergent VLSI Computing System—Extraction 45 3.4 Performance Study and Discussion 50 3.5 Further Research 50 3.6 Conclusion 59 References 59 4 An Overview of the Hierarchical Temporal Memory Accelerators 63 Abdullah M. Zyarah and Dhireesha Kudithipudi 4.1 Introduction 63 4.2 An Overview of Hierarchical Temporal Memory 65 4.3 HTM on Edge 67 4.4 Digital Accelerators 68 4.4.1 PIM HTM 68 4.4.2 PEN HTM 69 4.4.3 Classic 70 4.5 Analog and Mixed-Signal Accelerators 72 4.5.1 RCN HTM 72 4.5.2 RBM HTM 73 4.5.3 Pyragrid 74 4.6 Discussion 76 4.6.1 On-Chip Learning 76 4.6.2 Data Movement 77 4.6.3 Memory Requirements 79 4.6.4 Scalability 80 Contents vii 4.6.5 Network Lifespan 82 4.6.6 Network Latency 83 4.6.6.1 Parallelism 84 4.6.6.2 Pipelining 85 4.6.7 Power Consumption 86 4.7 Open Problems 88 4.8 Conclusion 89 References 90 5 NLP-Based AI-Powered Sanskrit Voice Bot 95 Vedika Srivastava, Arti Khaparde, Akshit Kothari and Vaidehi Deshmukh 5.1 Introduction 96 5.2 Literature Survey 96 5.3 Pipeline 98 5.3.1 Collect Data 98 5.3.2 Clean Data 98 5.3.3 Build Database 98 5.3.4 Install Required Libraries 98 5.3.5 Train and Validate 98 5.3.6 Test and Update 98 5.3.7 Combine All Models 100 5.3.8 Deploy the Bot 100 5.4 Methodology 100 5.4.1 Data Collection and Storage 100 5.4.1.1 Web Scrapping 100 5.4.1.2 Read Text from Image 101 5.4.1.3 MySQL Connectivity 101 5.4.1.4 Cleaning the Data 101 5.4.2 Various ML Models 102 5.4.2.1 Linear Regression and Logistic Regression 102 5.4.2.2 SVM – Support Vector Machine 103 5.4.2.3 PCA – Principal Component Analysis 104 5.4.3 Data Pre-Processing and NLP Pipeline 105 5.5 Results 106 5.5.1 Web Scrapping and MySQL Connectivity 106 5.5.2 Read Text from Image 107 5.5.3 Data Pre-Processing 108 viii Contents 5.5.4 Linear Regression 109 5.5.5 Linear Regression Using TensorFlow 109 5.5.6 Bias and Variance for Linear Regression 112 5.5.7 Logistic Regression 113 5.5.8 Classification Using TensorFlow 114 5.5.9 Support Vector Machines (SVM) 115 5.5.10 Principal Component Analysis (PCA) 116 5.5.11 Anomaly Detection and Speech Recognition 117 5.5.12 Text Recognition 119 5.6 Further Discussion on Classification Algorithms 119 5.6.1 Using Maximum Likelihood Estimator 119 5.6.2 Using Gradient Descent 122 5.6.3 Using Naive Bayes’ Decision Theory 123 5.7 Conclusion 123 Acknowledgment 123 References 123 6 Automated Attendance Using Face Recognition 125 Kapil Tajane, Vinit Hande, Rohan Nagapure, Rohan Patil and Rushabh Porwal 6.1 Introduction 126 6.2 All Modules Details 127 6.2.1 Face Detection Model 127 6.2.2 Image Preprocessing 128 6.2.3 Trainer Model 130 6.2.4 Recognizer 130 6.3 Algorithm 131 6.4 Proposed Architecture of System 131 6.4.1 Face Detection Model 132 6.4.2 Image Enhancement 132 6.4.3 Trainer Model 132 6.4.4 Face Recognition Model 133 6.5 Conclusion 134 References 134