ARM v7-M Architecture Application Level Reference Manual

534 Pages·2006·2 MB·English

ARM v7-M Architecture
Application Level
Reference Manual
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Copyright ©2006 ARM Limited. All rights reserved.
ARM DDI 0405A-01
ARM v7-M Architecture Application Level Reference Manual
Copyright ©2006 ARM Limited. All rights reserved.
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The following changes have been made to this document.
Change History
Date Issue Change
21-Mar-2006 A first beta release
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iv Copyright ©2006 ARM Limited. All rights reserved. ARM DDI 0405A-01
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Contents
ARM v7-M Architecture Application Level
Reference Manual
Preface
About this manual .................................................................................. x
Unified Assembler Language ................................................................ xi
Using this manual ................................................................................ xii
Conventions ........................................................................................ xiv
Further reading .................................................................................... xv
Feedback ............................................................................................ xvi
Part A Application
Chapter A1 Introduction
A1.1 The ARM Architecture – M profile .................................................... A1-2
A1.2 Introduction to Pseudocode ............................................................. A1-3
Chapter A2 Application Level Programmer’s Model
A2.1 The register model ........................................................................... A2-2
A2.2 Exceptions, faults and interrupts ...................................................... A2-5
A2.3 Coprocessor support ........................................................................ A2-6
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Contents
Chapter A3 ARM Architecture Memory Model
A3.1 Address space ................................................................................. A3-2
A3.2 Alignment Support ........................................................................... A3-3
A3.3 Endian Support ................................................................................ A3-5
A3.4 Synchronization and semaphores .................................................... A3-8
A3.5 Memory types ................................................................................ A3-19
A3.6 Access rights .................................................................................. A3-26
A3.7 Memory access order .................................................................... A3-27
A3.8 Caches and memory hierarchy ...................................................... A3-32
A3.9 Bit banding ..................................................................................... A3-34
Chapter A4 The Thumb Instruction Set
A4.1 Instruction set encoding ................................................................... A4-2
A4.2 Instruction encoding for 16-bit Thumb instructions .......................... A4-3
A4.3 Instruction encoding for 32-bit Thumb instructions ........................ A4-12
A4.4 Conditional execution ..................................................................... A4-33
A4.5 UNDEFINED and UNPREDICTABLE instruction set space .......... A4-37
A4.6 Usage of 0b1111 as a register specifier ........................................ A4-39
A4.7 Usage of 0b1101 as a register specifier ........................................ A4-41
Chapter A5 Thumb Instructions
A5.1 Format of instruction descriptions .................................................... A5-2
A5.2 Immediate constants ........................................................................ A5-8
A5.3 Constant shifts applied to a register ............................................... A5-10
A5.4 Memory accesses .......................................................................... A5-13
A5.5 Memory hints ................................................................................. A5-14
A5.6 NOP-compatible hints .................................................................... A5-15
A5.7 Alphabetical list of Thumb instructions ........................................... A5-16
Part B System
Chapter B1 System Level Programmer’s Model
B1.1 Introduction to the system level ....................................................... B1-2
B1.2 System programmer’s model ........................................................... B1-3
Chapter B2 System Address Map
B2.1 The system address map ................................................................. B2-2
B2.2 Bit Banding ....................................................................................... B2-5
B2.3 System Control Space (SCS) .......................................................... B2-7
B2.4 System timer - SysTick .................................................................... B2-9
B2.5 Nested Vectored Interrupt Controller (NVIC) ................................. B2-10
B2.6 Protected Memory System Architecture ........................................ B2-12
Chapter B3 ARMv7-M System Instructions
B3.1 Alphabetical list of ARMv7-M system instructions ........................... B3-2
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Contents
Part C Debug
Chapter C1 Debug
C1.1 Introduction to debug ....................................................................... C1-2
C1.2 The Debug Access Port (DAP) ........................................................ C1-4
C1.3 Overview of the ARMv7-M debug features ...................................... C1-7
C1.4 Debug and reset .............................................................................. C1-8
C1.5 Debug event behavior ...................................................................... C1-9
C1.6 Debug register support in the SCS ................................................ C1-11
C1.7 Instrumentation Trace Macrocell (ITM) support ............................. C1-12
C1.8 Data Watchpoint and Trace (DWT) support ................................... C1-14
C1.9 Embedded Trace (ETM) support .................................................... C1-15
C1.10 Trace Port Interface Unit (TPIU) .................................................... C1-16
C1.11 Flash Patch and Breakpoint (FPB) support .................................... C1-17
Appendix A Pseudo-code definition
A.1 Instruction encoding diagrams and pseudo-code ...................... AppxA-2
A.2 Data Types ................................................................................. AppxA-4
A.3 Expressions ............................................................................... AppxA-8
A.4 Operators and built-in functions ............................................... AppxA-10
A.5 Statements and program structure ........................................... AppxA-18
A.6 Helper procedures and functions ............................................. AppxA-22
Appendix B Legacy Instruction Mnemonics
Appendix C CPUID
C.1 Core Feature ID Registers ......................................................... AppxC-2
Appendix D Deprecated Features in ARMv7M
Glossary
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Contents
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Preface
This preface describes the contents of this manual, then lists the conventions and terminology it uses.
• About this manual on pagex
(cid:129) Unified Assembler Language on pagexi
(cid:129) Using this manual on pagexii
(cid:129) Conventions on pagexiv
(cid:129) Further reading on pagexv
(cid:129) Feedback on pagexvi.
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Preface
About this manual
This manual documents the Microcontroller profile associated with version 7 of the ARM Architecture
(ARMv7-M). For short-form definitions of all the ARMv7 profiles see pageA1-1.
The manual consists of three parts:
Part A The application level programming model and memory model information along with the
instruction set as visible to the application programmer.
This is the information required to program applications or to develop the toolchain
components (compiler, linker, assembler and disassembler) excluding the debugger. For
ARMv7-M, this is almost entirely a subset of material common to the other two profiles.
Instruction set details which differ between profiles are clearly stated.
Note
All ARMv7 profiles support a common procedure calling standard, the ARM Architecture
Procedure Calling Standard (AAPCS).
Part B The system level programming model and system level support instructions required for
system correctness. The system level supports the ARMv7-M exception model. It also
provides features for configuration and control of processor resources and management of
memory access rights.
This is the information in addition to Part A required for an operating system (OS) and/or
system support software. It includes details of register banking, the exception model,
memory protection (management of access rights) and cache support.
Part B is profile specific. ARMv7-M introduces a new programmer’s model and as such has
some fundamental differences at the system level from the other profiles. As ARMv7-M is
a memory-mapped architecture, the system memory map is documented here.
Part C The debug features to support the ARMv7-M debug architecture, and the programmer’s
interface to the debug environment.
This is the information required in addition to Parts A and B to write a debugger. Part C
covers details of the different types of debug:
(cid:129) halting debug and the related debug state
(cid:129) exception-based monitor debug
(cid:129) non-invasive support for event generation and signalling of the events to an external
agent.
This part is profile specific and includes several debug features unique within the ARMv7
architecture to this profile.
x Copyright ©2006 ARM Limited. All rights reserved. ARM DDI 0405A-01
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