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Architecture and operating system support for virtual memory PDF

177 Pages·2018·1.839 MB·English
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Series ISSN: 1935-3235 B H A T Synthesis Lectures on T A C Computer Architecture H A R JE E • L U S Series Editor: Margaret Martonosi, Princeton University T I G Architectural and Abhishek Bhattacharjee, Rutgers University Architectural and Operating System Support for Virtual Memory Daniel Lustig, NVIDIA A R Abhishek Bhattacharjee, Rutgers University C H Daniel Lustig, NVIDIA I T Operating System E C This book provides computer engineers, academic researchers, new graduate students, and seasoned practitioners T U an end-to-end overview of virtual memory. We begin with a recap of foundational concepts and discuss not R A only state-of-the-art virtual memory hardware and software support available today, but also emerging research L A trends in this space. The span of topics covers processor microarchitecture, memory systems, operating system N Support for D design, and memory allocation. We show how efficient virtual memory implementations hinge on careful O P hardware and software cooperation, and we discuss new research directions aimed at addressing emerging E R problems in this space. A T Virtual memory is a classic computer science abstraction and one of the pillars of the computing revolution. IN It has long enabled hardware flexibility, software portability, and overall better security, to name just a few of G Virtual Memory S its powerful benefits. Nearly all user-level programs today take for granted that they will have been freed from YS T the burden of physical memory management by the hardware, the operating system, device drivers, and system E M libraries. S U However, despite its ubiquity in systems ranging from warehouse-scale datacenters to embedded Internet P P of Things (IoT) devices, the overheads of virtual memory are becoming a critical performance bottleneck today. O R Virtual memory architectures designed for individual CPUs or even individual cores are in many cases struggling T F to scale up and scale out to today’s systems which now increasingly include exotic hardware accelerators (such O R as GPUs, FPGAs, or DSPs) and emerging memory technologies (such as non-volatile memory), and which V run increasingly intensive workloads (such as virtualized and/or “big data” applications). As such, many of the IR Abhishek Bhattacharjee T fundamental abstractions and implementation approaches for virtual memory are being augmented, extended, U A or entirely rebuilt in order to ensure that virtual memory remains viable and performant in the years to come. L Daniel Lustig M E M O About SYNTHESIS R Y TDbohigoisik tsva olp lruLomivbierd aeisr yca o opnfrc iinsEteen, dgo ivrniegeriesniraoilnn gp o rfea sane dnw toaCtrikoo mnthspa uot tfae pirmp eSpacorirset aninnct et .hr ee s eSSayyrnnctthhh eeassniidss M O development topics, published quickly, in digital and print formats. R G A N Synthesis Lectures on & C Computer Architecture L A Y store.morganclaypool.com P O O L Architectural and Operating System Support for Virtual Memory Synthesis Lectures on Computer Architecture Editor MargaretMartonosi,PrincetonUniversity FoundingEditorEmeritus MarkD.Hill,UniversityofWisconsin,Madison SynthesisLecturesonComputerArchitecturepublishes50-to100-pagepublicationsontopics pertainingtothescienceandartofdesigning,analyzing,selectingandinterconnectinghardware componentstocreatecomputersthatmeetfunctional,performanceandcostgoals.Thescopewill largelyfollowthepurviewofpremiercomputerarchitectureconferences,suchasISCA,HPCA, MICRO,andASPLOS. ArchitecturalandOperatingSystemSupportforVirtualMemory AbhishekBhattacharjeeandDanielLustig 2017 DeepLearningforComputerArchitects BrandonReagen,RobertAdolf,PaulWhatmough,Gu-YeonWei,andDavidBrooks 2017 On-ChipNetworks,SecondEdition NatalieEnrightJerger,TusharKrishna,andLi-ShiuanPeh 2017 Space-TimeComputingwithTemporalNeuralNetworks JamesE.Smith 2017 HardwareandSoftwareSupportforVirtualization EdouardBugnion,JasonNieh,andDanTsafrir 2017 DatacenterDesignandManagement:AComputerArchitect’sPerspective BenjaminC.Lee 2016 iv APrimeronCompressionintheMemoryHierarchy SomayehSardashti,AngelosArelakis,PerStenström,andDavidA.Wood 2015 ResearchInfrastructuresforHardwareAccelerators YakunSophiaShaoandDavidBrooks 2015 AnalyzingAnalytics RajeshBordawekar,BobBlainey,andRuchirPuri 2015 CustomizableComputing Yu-TingChen,JasonCong,MichaelGill,GlennReinman,andBingjunXiao 2015 Die-stackingArchitecture YuanXieandJishenZhao 2015 Single-InstructionMultiple-DataExecution ChristopherJ.Hughes 2015 Power-EfficientComputerArchitectures:RecentAdvances MagnusSjälander,MargaretMartonosi,andStefanosKaxiras 2014 FPGA-AcceleratedSimulationofComputerSystems HariAngepat,DerekChiou,EricS.Chung,andJamesC.Hoe 2014 APrimeronHardwarePrefetching BabakFalsafiandThomasF.Wenisch 2014 On-ChipPhotonicInterconnects:AComputerArchitect’sPerspective ChristopherJ.Nitta,MatthewK.Farrens,andVenkateshAkella 2013 OptimizationandMathematicalModelinginComputerArchitecture TonyNowatzki,MichaelFerris,KarthikeyanSankaralingam,CristianEstan,NilayVaish,and DavidWood 2013 v SecurityBasicsforComputerArchitects RubyB.Lee 2013 TheDatacenterasaComputer:AnIntroductiontotheDesignofWarehouse-Scale Machines,Secondedition LuizAndréBarroso,JimmyClidaras,andUrsHölzle 2013 Shared-MemorySynchronization MichaelL.Scott 2013 ResilientArchitectureDesignforVoltageVariation VijayJanapaReddiandMeetaSharmaGupta 2013 MultithreadingArchitecture MarioNemirovskyandDeanM.Tullsen 2013 PerformanceAnalysisandTuningforGeneralPurposeGraphicsProcessingUnits (GPGPU) HyesoonKim,RichardVuduc,SaraBaghsorkhi,JeeChoi,andWen-meiHwu 2012 AutomaticParallelization:AnOverviewofFundamentalCompilerTechniques SamuelP.Midkiff 2012 PhaseChangeMemory:FromDevicestoSystems MoinuddinK.Qureshi,SudhanvaGurumurthi,andBipinRajendran 2011 Multi-CoreCacheHierarchies RajeevBalasubramonian,NormanP.Jouppi,andNaveenMuralimanohar 2011 APrimeronMemoryConsistencyandCacheCoherence DanielJ.Sorin,MarkD.Hill,andDavidA.Wood 2011 DynamicBinaryModification:Tools,Techniques,andApplications KimHazelwood 2011 vi QuantumComputingforComputerArchitects,SecondEdition TzvetanS.Metodi,ArvinI.Faruque,andFredericT.Chong 2011 HighPerformanceDatacenterNetworks:Architectures,Algorithms,andOpportunities DennisAbtsandJohnKim 2011 ProcessorMicroarchitecture:AnImplementationPerspective AntonioGonzález,FernandoLatorre,andGrigoriosMagklis 2010 TransactionalMemory,2ndedition TimHarris,JamesLarus,andRaviRajwar 2010 ComputerArchitecturePerformanceEvaluationMethods LievenEeckhout 2010 IntroductiontoReconfigurableSupercomputing MarcoLanzagorta,StephenBique,andRobertRosenberg 2009 On-ChipNetworks NatalieEnrightJergerandLi-ShiuanPeh 2009 TheMemorySystem:YouCan’tAvoidIt,YouCan’tIgnoreIt,YouCan’tFakeIt BruceJacob 2009 FaultTolerantComputerArchitecture DanielJ.Sorin 2009 TheDatacenterasaComputer:AnIntroductiontotheDesignofWarehouse-Scale Machines LuizAndréBarrosoandUrsHölzle 2009 ComputerArchitectureTechniquesforPower-Efficiency StefanosKaxirasandMargaretMartonosi 2008 ChipMultiprocessorArchitecture:TechniquestoImproveThroughputandLatency KunleOlukotun,LanceHammond,andJamesLaudon 2007 vii TransactionalMemory JamesR.LarusandRaviRajwar 2006 QuantumComputingforComputerArchitects TzvetanS.MetodiandFredericT.Chong 2006 Copyright©2018byMorgan&Claypool Allrightsreserved.Nopartofthispublicationmaybereproduced,storedinaretrievalsystem,ortransmittedin anyformorbyanymeans—electronic,mechanical,photocopy,recording,oranyotherexceptforbriefquotations inprintedreviews,withoutthepriorpermissionofthepublisher. ArchitecturalandOperatingSystemSupportforVirtualMemory AbhishekBhattacharjeeandDanielLustig www.morganclaypool.com ISBN:9781627056021 paperback ISBN:9781627059336 ebook DOI10.2200/S00795ED1V01Y201708CAC042 APublicationintheMorgan&ClaypoolPublishersseries SYNTHESISLECTURESONCOMPUTERARCHITECTURE Lecture#42 SeriesEditor:MargaretMartonosi,PrincetonUniversity FoundingEditorEmeritus:MarkD.Hill,UniversityofWisconsin,Madison SeriesISSN Print1935-3235 Electronic1935-3243

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