Application-Specific Mesh-based Heterogeneous FPGA Architectures

164 Pages·2011·10.62 MB·English

by  Husain Parvez, Habib Mehrez (auth.)

Application-Specific Mesh-based Heterogeneous
FPGA Architectures

Husain Parvez • H abib Mehrez
Application-Specific Mesh-based
Heterogeneous FPGA
Architectures
Husain Parvez Habib Mehrez
Université Pierre et Marie Curie Université Pierre et Marie Curie
Paris VI, Laboratoire LIP6 Paris VI, Laboratoire LIP6
Départment SoC, Equipe CIAN Départment SoC, Equipe CIAN
4, Place Jussieu 4, Place Jussieu
75252 Paris 75252 Paris

France France
[email protected] [email protected]

ISBN 978-1-4419-7927-8 e- IS B N 978-1-4419-7928-5
DOI10 .1007/978-1-4419-7928-5
Springer New York Dordrecht He idelberg Lon don

© Springer Science+Business Media, LLC 2011
All rights reserved. This work may not be translated or copied in whole or in part without the written permission
of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA),
except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of
information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar method-
ology now known or hereafter developed is forbidden.
The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not
identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprie-
tary rights.
Printed on acid-free paper
Springer is part of Springer Science+Business Media (www.springer.com)
Foreword
Thisbookconcernsthebroaddomainofreconfigurablearchitecturesandmorespecifically
FPGAs.Differentissuesthatarethecentreofthisbookareveryessentialandareintended
toovercomethecurrentlimitationsofFPGAs,whichareexperiencingextremelyrapidand
sustaineddevelopmentforseveralyears.Infact,FPGAsofferaparticularlyremarkableflex-
ibilitybutsufferfromalevelofperformancethatcanbedisadvantageousforsomeapplica-
tionsintermsofsurface,speedorenergy.Thisworkpresentsseveralsignificantandoriginal
contributionsinordertoremovetheselimitationsbyfocusingespeciallyonsurfacemetric.
This book aims at exploring heterogeneous FPGA architectures dedicated to a given set
ofapplication circuits. Beyond architectureexploration, this work also presentsautomatic
FPGA"layout"generationflow,andanewcomponentcalledasanASIF"ApplicationSpe-
cificInflexibleFPGA",whichsignificantlyreducessiliconfootprintbycustomizingthear-
chitectureforagivensetofapplicationscircuits.Theimportanceandoriginalityofthecon-
tributionsmadeinthisworkrevolvearoundthisnewconceptofapplicationspecificrecon-
figurablecircuits,mainlythedevelopmentofanentiredesignenvironmentincluding:gen-
erationtools,floor-planning,placementandroutingadaptedtothecaseofheterogeneous
blocks.Carefulanalysisofresultsandthevalidationofproposedtechniqueshavealsobeen
observed.
ThemonographofthisbookisbasedonHusain’sdoctoralthesis.Itwasagreatpleasurefor
metosupervisehisthesis.Thisbookwillbeofspecialinterestforstudentsandresearchesin
thedomainofFPGAarchitecturesingeneral,andapplication-specificFPGAarchitectures,
heterogeneousFPGAarchitectures,andtheirautomatichardwaregenerationinparticular.
Prof.Dr.HabibMEHREZ
TeamLead,AnalogandDigitalIntegratedCircuitGroupat
System-on-ChipdepartmentofLIP6
ProfessoratUniversityofParis6(UPMC),Paris,France
v

Preface
1 Abstract
LowvolumeproductionofFPGA-basedproductsisquiteeffectiveandeconomicalbecause
theyareeasytodesignandprograminshortestpossibletime.Thegenericreconfigurable
resourcesinanFPGAcanbeprogrammedtoexecuteavastvarietyofapplicationsatmu-
tuallyexclusivetimes.However,theflexibilityofFPGAsmakesthemmuchlarger,slower,
and more power consuming than their counterpart ASICs. Consequently, FPGAs are un-
suitableforapplicationsrequiringhighvolumeproduction,highperformanceorlowpower
consumption.ThemainthemeofthisworkistoreduceareaofFPGAsbyintroducinghet-
erogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing ap-
plication specific FPGAs. Automatic FPGA layout generation techniques are employed to
decreasenon-recurringengineering(NRE)costsandtime-to-marketofapplicationspecific
heterogeneousFPGAarchitectures.
Thisworkinitiallypresentsanewenvironmentfortheexplorationofmesh-basedheteroge-
neousFPGAarchitectures.Anarchitecturedescriptionmechanismallowstodefinenewhet-
erogeneousblocks.Avarietyofautomaticandmanualoptionscanbeselectedtooptimize
floor-planningofheterogeneousblocksontheFPGAarchitecture.Theexplorationenviron-
mentlaterallowstotestdifferentbenchmarkcircuitsonthenewlydefinedheterogeneous
FPGAarchitecture.AnautomaticFPGAlayoutgeneratorispresentedwhichgeneratesatile-
basedFPGAlayoutforasubsetofarchitecturesgeneratedbyourexplorationenvironment.
Wehavesuccessfullytaped-outa1024Look-UpTablebasedmeshFPGAarchitectureusing
130nm6-metallayerCMOSprocessofST.
TheHeterogeneousFPGAexplorationenvironmentisfurtherenhancedtoexploreapplica-
tion specific FPGAs. If a digital product is required to provide multiple functionalities at
exclusivetimes,eachdistinctfunctionalityrepresentedbyanapplicationcircuitisefficiently
mappedonanFPGA. Later,the FPGAisreducedforthegiven setofapplication circuits.
ThisreducedFPGAisproposedandtermedhereasanApplicationSpecificInflexibleFPGA
(ASIF).Themainideaistoperformprototyping,testingandeveninitialshipmentofade-
sign on an FPGA; later it can be migrated to an ASIF for high volume production. ASIF
generationtechniquescanalsobeemployedtogenerateasingleconfigurableASICcorethat
canperformmultipletasksatdifferenttimes.AnASIFfor20MCNCbenchmarkcircuitsis
foundtobe82%smallerthanatraditionalmesh-basedunidirectionalFPGArequiredtomap
anyofthesecircuits.AnASIFcanalsobereprogrammedtoexecutenewormodifiedcircuits,
vii
viii Preface
butunlikeFPGAs,ataverylimitedscale.AnewCADflowispresentedwhichcanmapnew
applicationcircuitsonanASIF.AnautomaticASIFhardwaregeneratorisalsopresented.
2 Dedication
Dedicatedtomyparents,andtoScamoail,Hasan,OmerandAsma.
HusainParvez
3 Acknowledgments
ThisbookisbasedonmyPhD.thesisatLIP6/UniversiyPierre&MarieCurie(UPMC).Iam
highlyindebtedtoProfessorHabibMehrezforsupervisingmythesis.Iamalsogratefulfor
hiscontinualtechnicaladvice.IamextremelythankfultoProfessorGuyGogniat,andDr.
GillesSassatelli,forreviewingmythesisandfortheirvaluablecomments.
I am immensely grateful to Dr. Hayder Mrabet and Dr. Zied Marrakchi for providing de-
tailedandinsightfultechnicaladvice.Thisthesiswouldnothadbeenpossiblewithouttheir
supportandguidance.IamalsothankfultoDr.AndréTissotandDr.NicolasFelfortheir
technicalguidanceinthetape-outofFPGAchip.
IwouldalsoliketothankAssosiateProfessorHassanAboushadyformotivatingmetopub-
lishmyPhD.workintheformofthisbook.
Contents
Foreword v
Preface vii
ListofFigures xiii
ListofTables xvii
1 Introduction 1
1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.2 Application-specificinstruction-setprocessor(ASIPs) . . . . . . . . . . 3
1.1.3 ApplicationSpecificIntegratedCircuits(ASICs) . . . . . . . . . . . . . 3
1.1.4 Structured-ASICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Motivationandcontribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 ExplorationenvironmentforheterogeneousFPGAArchitectures . . . 5
1.2.2 AutomaticFPGAlayoutgeneration . . . . . . . . . . . . . . . . . . . . 5
1.2.3 ASIF:ApplicationSpecificInflexibleFPGA . . . . . . . . . . . . . . . . 6
1.2.4 AutomaticASIFhardwaregeneration . . . . . . . . . . . . . . . . . . . 6
1.3 FieldofApplications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 BookOrganization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Stateoftheart 9
2.1 IntroductiontoFPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 ConfigurableLogicBlock . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2 RoutingNetwork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.3 SoftwareFlow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 ResearchtrendsinFPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.1 VersatilePacking,PlacementandRouting,VPR . . . . . . . . . . . . . 19
2.2.2 Madeo,aframeworkforexploringreconfigurablearchitectures . . . . 20
2.2.3 AlteraArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ix
x Contents
2.2.4 AlteraHardCopy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.5 ConfigurableASICCores(cASIC) . . . . . . . . . . . . . . . . . . . . . 24
2.2.6 FPGAbasedprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.7 AReconfigurableArithmeticArrayforMultimediaApplications,CHESS 26
2.2.8 ReconfigurablePipelinedDatapaths,Rapid . . . . . . . . . . . . . . . 26
2.2.9 Time-MultiplexedSignals . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.10 Time-MultiplexedFPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3 HeterogeneousFPGAExplorationEnvironment 31
3.1 IntroductionandPreviousWork . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2 ArchitectureExplorationEnvironment . . . . . . . . . . . . . . . . . . . . . . . 32
3.3 ArchitectureDescriptionMechanism . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4 SoftwareFlow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.4.1 Parsers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4.2 Placer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.4.3 Router . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.5 Floor-planningTechniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.6 AreaModel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.7 ExperimentationandAnalysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.7.1 ExperimentalMethodologyusingCommonArchitecture . . . . . . . . 48
3.7.2 BenchmarkCircuitsforCommonArchitecture . . . . . . . . . . . . . . 49
3.7.3 ResultsandAnalysisforCommonArchitecture . . . . . . . . . . . . . 51
3.7.4 ExperimentalMethodologyusingIndividualArchitectures . . . . . . 56
3.7.5 BenchmarkCircuitsforIndividualArchitectures . . . . . . . . . . . . . 56
3.7.6 ResultsandAnalysisforIndividualArchitectures . . . . . . . . . . . . 56
3.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4 FPGALayoutGeneration 61
4.1 IntroductionandPreviouswork . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 FPGAGeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.2.1 Open-sourceVLSItools . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.2.2 Tilebasedapproach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.2.3 Netlistgeneration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.2.4 TileLayout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.2.5 Powerrouting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66