Analysis and Design of Analog Integrated Circuits

893 Pages·2001·21.52 MB·English

by  Gray

OF
ANALOG
INTEGRATED ==

CIRCUITS
ANALYSIS AND DESIGN
OF ANALOG INTEGRATED
CIRCUITS

Fourth Eifion
ANALYSIS AND DESIGN
OF ANALOG INTEGRATED
CIRCUITS

Fourth Edition

PAULR. GRAY
University of Cationic, Berates

PAUL J. HURST

Daw

ROBERT G. MEYER
Uatrersity of Cultoraa, Berketes

@

JOHN WILEY & SONS, INC.

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Preface

{In the 23 years since che publication of the frst edition of this book, the lield uf andlog
integrated circuits hn developer and matured. The initia] groundwork was laid in ple
technology, followed! hy 4 rapicl evulafion nf MOS analog integrated eivcnits, Purther-
mute, BYCMOS tcelmulogy (incorporating both bipolar and CMOS devices ou one chip}
has emerged as 2 serious contender tothe original technologies. A key issue is thil CMOS
‘wobaotogies finve become dominaut in building digital circuits beeause CMOS digital
revils ae. araller andl cisniate lens pines than Uneie bipolar counterparts, To zeduee
System cus! anal power dissipatinn, analog and digital circuits are now often integrated
together, providing a strong osanomic inccative to use CMOS-corapatible analog ciecuits
‘Asa resul, an impartantqucstion in many applications is whelher to use pure CMOS or
BiCMOS technology. Alchough somewhat roore expensive 10 fabricate, BICMOS stlows
the designer lo use both bipolar au) MOS devices tp thelr best advantage, and also al

Jews innovative combinitions ofthe charleristice of both devices. Tu audition, BICMOS
‘can seduce the design time by allowing dircet use of many existing cells in zealizing a
sven analog circuit function. On the otber hand, the main advantage of pure CMOS is
‘hati offers the Lowest overall cost. Twenty years ago, CMOS techmiigies were only fast
ccnough to support applications at die Frequencies. However, Ire wintiuing reduction of
the minimum feature size fm musgrated-eueuit (IC) tectunelogiey has really increased he
maximum operating frequencies, aud CMOS technelogics lave become fast enough for
many new applications as a result. For example, the requited bandwidth in videw appli
cationa is nbow 4 ME, requiring bipalar technologies as recently as 1 years ave. Novy,
bowever, CMOS can easily acconauiodate the requiral hanwallh te video and 18 oven
being used for radio frequency spptications.

In this Fourth edation, we have combined the consideration of MOS and bipclar cir
‘cuits nto u unified ueatmenl that also invludes MOS-bipolar connections madz possible
by BICMOS technology. We have waitlen thiy edilion sa thal insiruclurs vam easly we
lect capics related 19 only CMOS circuits, only bipolar ciciity, ora zoinbinatinn al oh.
‘We helieve thar it has became incteasing|y important for tho analog circuit designer 10
have a (uimnugh appreciation o the similarities and diffcrences betwen MOS and bipolar
devices, and to beable to design with either one where this is appmprice

Since the SPICE computer analysis programa i< mow really availble kv virtually
all electrical engineering studers and professimals. we Inve wluled vauaasive use oF
SPICE in this edition, particularly as an integral part of many problems. We have used
‘vompuler analysis as iL is most commonly emuployed io the enginzering design process
both asa more accurate check on haed calewlntions, and alse as.a tonto examine enmiplex
circuit behavior beyond the scape of band wnalysis In he prublean seis, we Mave ala
cluded a number of npen-ended design prablems to expose the read (real-world situa
tions where whale range of eieuil solutions may he found. satisfy a given porfonnance
specication

This book is intended to be usefil both #8 feat lor sluents aud ay eeferemee bok
{for practicing engineers. For class use, each chapter includes wemny worked pmobems; Wie
problem sels al the end of each chapter iustrate the practical apglieatiovs of the material
fn the ext. All dhe authins ave hail extensive industrial experience in EC desiga 9s well
vill Puce

as ine teuching oFemases on this subject, and this
~CWeal mntetial und bs the problera sets,

‘Although this book is concerned larzely with che analysis and design of ICs, 8 cous
‘rable smcunt of muteriol is als included en applications, [a practice, hese two subjects
are dsely Jinked, and y Loogdedge of hoth #5 essonlial for designers snd users of ICs,
The later compose tke lager group by far, anal we Leliove thst a working knowledge a
TC design 4s a arcat advantage to an 1C user, Thus w particularly apparent when the nsec
rust ctcose from among a number of competing design to satisfy a particulst need. Au
vonderstandiny of the IC snc is taem useful in evaluating the eolutive Wesicability af che
different designs under extremes of enviranment Grin tne presence 1 variations in spay
vvollags, In additiow, the IC. user i ina unach better position tn inicspme! 9 manofaeleets
dota jfhe 0 she has a working kaowledge-of the imomal eyeration of tue integrased creull,

The vonlenls of this baok stein Jargety fram courses en analog inlegrated circuit even
al the University of Calitunia at the Berkeley and Davis eampuscs, ‘Tv courses are on-
ddovgiaduate clectives aul frsl-ycar graduate courses. The hack i shtctured sa that i
call be used ag ta basiv cext (ur a seynenoy of such courses, The auure adsanevel mate
il iz Gund of the end a¥ ench chuptec or in an appendix xo thats first cousrc in analog
meget! creuits can ent this snaterial wihout loss of continuity: An outline of each
chapter is ewer below kugethcr with suggestions lir mauerial by he covered im such w fits
course. It is assumed that the course consists of Umree huts vf lecture per week ver
I Scseek semester and that the susients have 0 working knowlsdge of Laplace cranstoams
and frequeney-domtain cireuic analysis. His also apscimed thatthe students have Aad an
inuoductory course inelectionics 50 Thal ey abe fgiliar wath the principles of Iransislor
‘operation and with the fanetinning bf simple analag cincins, Thloss othersise stated, each
‘chapter seqqites three te ious Sectaro hawrs wo coves

Chapter 1 contains a summary of bipolar cransistex and MOS tramsistor device pv sic
‘We sugges! spenling one Week. oa select tapes (rom this chapter, the choice nf Sypies
dopending om the hackyrinel nf the stodeuts. Fhe material af Chapters 1 andl 2 is quite
‘important in 1C design because there is Signditant interaction between citeut and desis
design, a6 will bo seen in Tater chapters, A chorongh understanding of ihe influence of
dovige fubricatin on deviey eharacteristes 1 ensentia

‘Chapice2 is eaucermed withthe echnology ol IC Fabvieatinn sand is kgely descriptive.
‘One Jeeture on this material should suffice if ehe students arc ossignd to ead the ebayer.

‘Chapter 3 deals with the characisistics of elementary wransiter eumacetions, The mae
terial on one-transister armpliiats shoul he a foview far snudenra atthe senior and grach
ate levels and car he ansiyncel as reading. The Seclion un hwt-inensistor aupliGers can be
rovered in abool three boars, with greatest cmpbssis on differential pasts, The matorial on
device. muismaich cflects differential oraplliers can be covered 1a the exten thar tunic

isrefloced in the cbaive

allows,
Jn Chapter 4. the important opies of current nierors and active loves are considered
‘There condgucations ars basiv brilding blocks in encdeun while IC desigu, und this muse

levial shuld be covered in ful, withthe exceplion of the material un banslgap reforcness
and the snstaial in dle appendices,

Chapter 5 is zoncemed wilh output stages ancl metlews of celivering culpa power Ie
a Toad, Intzgeared-cveuit realizations of Class A, Clase B, st Clase AB output sliges sre
escribed, as well as rocthnds of oulpot-stuge protection. A selection of topics from this
hapter siculdl be covcred.

(Chapter 6 deals with the desig of perational ampli lies lop ns}, Dlusteative cxain-
ples uf de and av analysis in both MOS and bapolar op wraps are peafrmed in deta), and
The Limitations of the basic wp aunps are described, Ta design af op ampa with improved
Profena ix

charactcristies in beth MOS and bipolar technologies is considered, ‘Ihis key chapter on
amplifier design requires at Ieast six houce,

‘Ia Chaplet 7, tbe frequency response of ampliliers i+ considered. The-ze10-value time-
constant technique is introduced for the calculations of the ~3-4B frequency of complex
circuits, The maletial of this chapter should be considered in ful

‘Chaptcr 8 desorites the analysis of teedhack, circuits. Two different types of analysis
ate presented: rn-port and relurr-ralia analyses. Either approsch should be cavered in
fall With the section on voltage regulators assigaed as reading.

Chapter 9 deals with the Lrequency response and stability of Feedback circuits and
should be eoveral upto the section an rootlocus, Time ay not permita detailed discussion
of rot locus, but some introdnction to this tnpic can he given.

Ta a 15-week semester, coverage of the above material leaves about nwo weeks lar
Chapters 10, 11, and 12. A selection of topics from these cbuplers van be chosen ax follows.
Chapter 10 deals with nonlinear analng vitcuits, and portions of this chapter up t Section
10,3 cowid be eivered in a fiest course. Chapter 11 is a compretensive treatment uf nuise
in totegrated circuits, and material up to and including Section 11.4 is suitable. Chapger 12
deseribes folly differential operational sunplifirs aad common-mode feedback and may
he hest suited for a scvond course,

‘We are grateful to she following colleagues for their suggestions for amd/or eval-
uation of this edition: R. Jacob Baker, Bomhard EB, Boser, A. Paul Brokaw, Jutin N.
(Churchill, David W. Cline, Ozan E, Eragon, Johm W. Fatlarusu. Weinan Gao, Edwin W.
Grceneich, Alex Cros-Balthazard, Tunde Gyuries, Ward J, Helms, Timothy H. Ho, Shafiy
Mi. Jamal, Jahn P. Keaue, Haideh Khorcamabadi, Pek-Kim Law. Thamas W. Matthews,
Keishnaswamy Nagaraj, Khali] Nujall, Burivaje Nikolig, Robert A. Pease, Lawrence T.
Pileggi, Edgar Sinchey-Sinencio, Bang-Sup Song, Richard R. Spencer, Hric J. Swanson,
‘Andeew ¥. T. Sacto, Yannis P. Teividis, Srikanth Vaidianathan, T. R, Viswanathan, Chomg-
Kung, Wang, and Dong Wang, We art also grateful we Keoneth €. Dyer for allowing us (0
use on the eover uf tus book die phomngraph of un imteyrated circuit he designed and to
Zoe Maclowe for her assistance with wun processing. Pinally, we would Ike to thank the
people at Wiley and Publication Servioss for their efforts in producing this fousth cdition,

‘The material in this book has beea greally influenced by aur association with Donald
(©. Pocerson, und we acknowledge his contributions.

Berkeley and Davis, CA, 2008 Pasd R. Gray
Paal J. Hurst
‘Stephon H. Lewis
Robert G, Mayer
Contents

Models for integrated-Citeult Active
Devices 1
AJ lneduetion 1

1.2 Pepletion Region ofa px Juneliva 1
121 Degiz 5
1.22 Iwoliva Breskduwn &

1.3 Large-Signal Behavior of Bipolar
Tranisters ¥
165.1 Large Signal Medele 9 tts

Furwari-tcuve Region 9
132. Eteets af Collector Varage
{arge-signsl Characteristics i the
Foneami-Aative Region LE
sos gc€ Inverse Active

Repions 16

1.34 Trassster Hyeakslown Vattes
a

Dependence of Tranesrer Current

Gai Be ou Oparaing Conditions

wll Signal Models of Bipolar

‘Transistors 26

Region Caps

LAL Transeonduetanss 27
12 Bace-Chargung Capciaawwe 28
14a topu, Resisance 2
144 Quique, Resistance 29
144 Basie Small Sigaa! Mev ofthe
Bipula Teensisce 30
‘Collevtor Base Resistance 20
Parasile Pemeals in he
Small-Sigual Mudel 31
148 Specification of T
Frequency Response 34
LS Large Signal Behavior af
Metal- Oxide Semicondvctot
Fielt-Bileet Tnusiswors 38
15.1 ‘nunaler Charsetersties ef MOS
Devine

16

19

Al

Ceuyurson of Opztaling Regions
of Ripolat and MOS Traut
as

[Decomposition af Gate Seurce
Woinngs 37

‘Threshold Tempeuluse
Dependence

MOS Tievice Vollage J smtatiens
a

Small Signal Madate of the. MOS
Tramisuas 49

16
163

163
Le
168

Mite
167

1s

Transennvtnctmee 30
Tauinsie Cats-Snnroe aud

Catz-Drsin Capaczance 54
pt Resiscansy
Omut Resisauee $2

ARasie Secu] Signal Model of the
MOS Teuister #2

Rody Temwumiuclince 53
Parasius Elaucate i the
SmatlSigual Mule 24
M08 Tiauister Fesqueiey
Response £3

Short Chammel Fffects in MOS
Transistor. $8

nat
12

wa

Sooeiny Sicuation ten Ge
Hvizeusa: Fic $9
Tounceonduetance and Tavs
Fequacy 65

Mobility Degradation from the
Neuwcal Fok! os

Weak Inversion in MOS Tunsistaes

65
rad

La

Basia
66

“Trmssocstuctance ant Fra;sition
Fraguency in Weak Inversion 68

nrc ics Weak Cavern,

Substrate Current Flow in MOS
Transistors 71

Sumeccy of Aut

Device

Parameters. 7%
ipoker, MOS, and BICMOS

Integrated-Circuil Technology 7%

21 Inwoduetion 78

2.2 Basie Processes in Invegrated
Fabrication 79

221. Flectrcal Resivivity nf Silicon
8

Solid-State Diffusion 80

Elootical Propo of Difused

Layers 82

Photclikegraphy 4

Epilinial Giowalh 25

Jor. implancacion $2

Toeal Oxidation 87

Polysilicoe Deposition #7

23 High-Voltage Bipolar
Integrated-Circuit Fabrication #8

24 Advanced Bipolar Intograwd-Circuit
Fabccation 92

25 Active Devices in Bipolar Analog
Iucgeated Ciscuits 9

it

25.1 tutegrsted-Cizcul apa Transistor
6
25.2 Imeyeaed-Cicuit pap ‘ranastors
107
2.8 Passive Compiments in Bipolar

Imtegeated Cirevite 118
246.1 Diffised Resistors 115
2.62. tpitasial and Enitosin Pinel

Resins 119

Lbs Integrated Circuit Capacrtors 120
264 Zace Diol 121
26S Munetion Diudes 122

2.7 Modifications to the Pasie Bipolar
Provest 123

Dielectvc Fnlation

Goxopatible Processing tot

Bigh- Performance Active Devices

ta

High-Pesiocmance Possive

Components 127

28 MOS Imegtated-Circuit Fabrication
fred

29° Active Devices in MOS Integrated
CSreuils Tat

contets ai
29
292
2938

Channel Tamsisions 131

pehannel fans 141

Depleven Neviess 142

294 BipelarTesisors 1-2

Passive Components in MOS

Technology 14

BAD Restor: Mt

2102 Cepocitas in MOS Techaicgy
M5

23 Latcup ia CMOS Techeslogs
1a

21 BICMOS Technology 150

2.32 Houerojunotion Bipolar Temaststore
L

Inserconncet Delay L

24 Reananies of Imeprated-Circait
Fabricatioa 154

2.141 Yield Consderaioas in
lutegiatos-Cucnit Fatecetion
154

2.14.2 Case Consiecatons in
Snlogtated rc Taiator,
15

Packaging Considerations or

Inegrated Crews 139

ZAG Mezsmunn Hour Dissipation 139

3.2 Relay Chraderanon m
Invzgrated ClscitTaskaging 162

AI SPICE ModeLParametes Biles 163

Single-Transistor and Muliple-Tensistor
Armpitiars 170

3.1 Device Model Sclection for
Aprraximate Anulysis of Analog
Chreuits 172

3.2 Two-Port Modeling of Ampliiers 172
Basie Single-Transistor Amplifier

Stages 14

33.1 Common miter Configuratina
U5

352. Crmman-Snuce Configuration
ny

3 Comme Base Configuration 183

334 Commontiate Canhgurntion 186