Table Of ContentANALOG SIGNAL PROCESSING
by
Peter B. Aronhime
University of Louisville
F. W. Stephenson
Virginia Polytechnic Institute
& State University
A Special Issue of
ANALOG INTEGRATED CIRCUITS
AND SIGNAL PROCESSING
An International Journal
Vol. 6, No. 3 (1994)
SPRINGER SCIENCE+BUSINESS MEDIA. LLC
Contents
Special Issue: Analog Signal Processing
Guest Editors' Introduction ....................................... P. B. Aronhime and F. W. Stephenson
Statistical Design
Global Design of Analog Cells Using Statistical Optimization Techniques ............................. .
. . . . . . . • . . . . . .F . Medeiro, R. Rodrfguez-Macfas, F. V. Fernandez, R. Dominguez-Castro, J. L. Huertas and
A. Rodrfguez-Vdzquez 3
DDA·Based Circuits
A Multiple Input Differential Amplifier Based on Charge Sharing on a Floating-Gate MOSFET .......... .
. . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .K . Yang and A. G. Andreou 21
Design and Applications of a CMOS Analog Multiplier Cell Using the Differential Difference Amplifier ...
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S.-C. Huang and M. Ismail 33
Optimization Techniques
On the Optimal Design of Switched-Capacitor Filter Circuits for Analog and Mixed-Signal Integrated Circuit
Realization ......................................................... N. C. Gustard and R. E. Massara 43
Optimal Gain Overdesign in Analog Filters .........•.............. A. C. M. de Queiroz and L. P. CaMba SS
Filter Design
A 7.2 GHz Bipolar Operational Transconductance Amplifier for Fully Integrated OTA-C Filters .......... .
. . . . . . . . . . . . . . . . . . . . . . . . . • . . • • . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M. Atarodi and J. Choma, Jr. 67
Current-Mode Synthesis Using Node Expansion Techniques ................... M. Desai and P. Aronhime 19
Macromodeling
Nonlinear Macromodeling with AWE ...................................... R. J. Trihy and R. A. Rohrer 89
ISBN 978-1-4419-5147-2 ISBN 978-1-4757-4503-0 (eBook)
DOI 10.1007/978-1-4757-4503-0
Llbrary of Congress Cataloglng-in-Publlcation Data
A C.I.P. Catalogue record for this book is available
from the Library of Congress.
Copyright © 1994 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers. Second Printing in 1998
AII rights rescrved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted in any form or by any means, mechanical, photo
copying, recording, or otherwise, without the prior written permission of the
publisher, Springer Science+Business Media, LLC
Printed an acid-free pap er.
Analog Integrated Circuits and Signal Processing, 6, 177-178 (1994)
C1 1994 Kluwer Academic Publishers, Boston.
Editorial
This special issue was conceived in Detroit during the 36th Midwest Symposium on Circuits and Systems. We
were asked by Editor-in-Chief Mohammed Ismail to select a collection of analog papers from those presented at
the conference and seek to have the authors develop them further for publication in this special issue.
It seemed to us quite appropriate that we undertake this task as a technical challenge as well as a means of
recognizing the unique role which the Midwest Symposium has played for the past thirty-nine years. It is the oldest
conference devoted to circuits and systems and affords a convenient form for the presentation of papers by graduate
students as well as by faculty and engineers from the non-academic arena. Furthermore, despite its somewhat
restrictive title, the Symposium has been held in many locations outside its original Midwest home. In recent years,
conferences have been held in Puebla (Mexico), Calgary (Canada), Monterey (California), Louisville (Kentucky),
Lafayette (Louisiana) and Washington, D.C. Future venues include Rio de Janeiro (Brazil) and Davis (California).
Of course, all of these conferences were, or will be, located in the midwest section of the town or city I
We carefully reviewed many papers presented in Detroit and decided that we must restrict our pool to those of an
analog nature. Furthermore, the papers needed to address something broader in scope and on a topic lending itself
to a full length journal paper. Our final selection loosely falls within our chosen title of Analog Signal Processing,
but we ask the reader's indulgence on this issue. More important to us has been the need to select a solid group of
analog-related papers which represent the breadth of topics covered in a variety of sessions in Detroit.
Several papers address the questions of cell design for CMOS applications. Medeiro et al. describe statistical
optimization for the design of complex analog cells while Yang and Andreou develop the lossless property of an
MOS floating gate into circuits having potential use as analog signal processing building blocks. By contrast, Huang
and Ismail discuss the design of a differential difference amplifier with application as a basic block in a simple
four-quadrant multiplier. In a further paper on analog design, Gustard and Massara use a switched-capacitor case
study to illustrate the usefulness of numerical optimization techniques in the generation of silicon-level layout for
analog functional modules from high-level specifications.
Filter design is featured in three oft he contributions, but in distinctly different ways. de Queiroz and CaiOba discuss
an optimal approach to the overdesign of gain-shaping filters, while Atarodi and Choma present a transconductaJtce
amplifier for use in active integrated filters operating at cut-off frequencies greater than 200 MHz. Finally, Desai
and Aronhime propose a method for the node expansion of passive prototypes from which may be derived a series
of oscillators and active filters.
The paper by Trihy and Rohrer is quite general and offers an approach for the simulation of nonlinear (linearized)
circuits. Using an asymptotic waveform evaluation, the paper offers strategies for macromodeling nonlinear circuits.
In conclusion, we wish to acknowledge the assistance of Dr. Jatindar Bedi, ECE Department, Wayne State
University, who served as Publications Chairman of the 36th Midwest Symposium. Dr. Bedi was extremely helpful
in providing us with pre-publication copies of several papers. In addition, we acknowledge the work of Dr. Michael
Polis (currently Dean of Engineering at Oakland University), General Chairman of the 36th Midwest Symposium
and other Operating Committee members, Dr. Harpeet Singh and Dr. Feng Lin(both at Wayne State University), Ben
Behera (Aero Service Corp.), Dr. Majid Ahmadi (University of Windsor), Dr. Nader Boustany (General Motors),
and Dr. Magdy Bayoumi (University of Southwestern Louisiana) for their efforts in organizing the Symposium.
Peter B. Aronhime
F. W. Stephenson
178 Aronhime and Stephenson
~ ;)~'J\11', the University of Durham {UK) and a Ph.D. in Electrical En
,~,. i gineering, 1965, at the University of Newcastle upon Tyne
{UK). Dr. Stephenson has been Dean of the College of Engi
neering at Virginia Tech since June 1994. From 1990-1994
he was Professor and Head of The Bradley Department of
Electrical Engineering at the same school. Previously, from
1986-1990, he was Associate Dean for Research and Gradu
ate Studies in the College ofEnglneering. In addition, he was
t~ the founding Director of the Virginia Tech Hybrid Micro
t. electronics Laboratory and co-founder of the Virginia Tech
Student Chapter of ISHM, the largest in the nation with 140
Peter Aronhlme received the B.E.E. degree from the Uni members: He has held industrial appointments with Welwyn
versity of Louisville in 1962 and M.S. and Ph.D. degrees Electric and the Microelectronics Division ofElectrosil, both
from the Colorado State University in 1964 and 1971. He has in England. While with Electrosil, he worked on the applica
held engineering positions with Bell Laboratories in Winston tions of both monolithic and hybrid integrated circuits. His
Salem, NC, and Hughes Aircraft in Fullerton, CA, and he has main research interests are in the areas of hybrid microelec
held academic positions with Tri-State University In Angola, tronics, RC active and switched-capacitor filter design. Prior
IN, and Jllinois Institute of Technology in Chicago. In 1976 to joining Virginia Tech In 1978, he taught at the Universities
he joined the University of Louisville, where he is Professor of Hull {UK) and Rochester, NY, where he was the RT French
of Electrical Engineering and Coordinator of the Computer Visiting Professor in 1976-77. He Is the co-author of Lin
Science and Engineering Ph.D. Program. In 19g7 he was a ear Microelectronic Systems, Macmillan, 1973, and Active
visiting professor at Colorado State University. His research Filters for Communications and Instrumentation, McGraw
interests include network theory, computer-aided circuit anal Hill {UK), 1979, and the editor of RC Active Filter Design
ysis/design/testing, modeling and instrumentation. Dr. Aron Handbook, John Wiley & Sons, 1985. He has published re
hirne is a member of Eta Kappa Nu, Sigma Xi, Phi Kappa search results in such journals as IEEE Transactions (CHMT
Phi, and Omicron Delta Kappa. and CAS), Tnt. Journal of Circuit Theory and Applications,
Microelectronics, and others. Dr. Stephenson is a member
of HKN, Tau Beta Pi, ODK, a Fellow of the Institution of
Electrical Engineers (lEE), and a Fellow of the Institute of
Electrical and Electronic Engineers (IEEE).
F. William Stephenson is a native of Newcastle upon Tyne,
England, earned a B.Sc. in Electrical Engineering, 1961, at
2
Analog Integrated Circuits and Signal Processing, 6, 179--195 (1994)
0 1994 Kluwer Academic Publishers, Boston.
Global Design of Analog Cells Using Statistical Optimization Techniques
F. MEDEIRO, R. RODRfGUEZ-MACiAS, F. V. FERNANDEZ, R. DOMiNGUEZ-CASTRO,
J. L. HUERTAS AND A. RODRfGUEZ-VA ZQUEZ
Dtpl. of Analog Circuit Dtslgn, Ctntro NaciDnal tk Mlc,.ltctrdnlu, Edlftclo CNM, Avda. Rtlna Mtrr:tdts ••. .
41012-Sml/a, SPAIN, FAX 34' 4624,06, Plumt 34 '4239923
angelllcnm.us.e~
Abstract. We present a methodology for automated sizing of analog cells using statistical optimization in a simula
tion based approach. This methodology enables us to design complex analog cells from scratch within reasonable
CPU time. Three different specification types are covered: strong constraints on the electrical performance of the
cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a
bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique
is also presented to yield designs with reduced variability in the performance parameters, under random variations
of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors
are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed
methodology.
1. Introduction connection of sub-blocks (differential pairs, current
mirrors, etc.), each of which can be expanded hier
The design of analog VLSI building blocks, and in archically down to the device-level. Tools also dif
general the design of any integrated circuit, comprises fer among themselves depending on the sizing strategy
three major steps. First, a suitable schematic must be used. In some approaches, the sizing process is re
selected. Then this schematic must be sized to com duced to a constrained optimization problem [6, 8]; in
ply with required performance specifications on gain, others, sizing is performed by following specific de
bandwidth, slew-rate, etc., as well as to meet design sign plans for each topology, previously developed by
objectives regarding area, power consumption, etc. Fi expert designers and stored in the tool database [1, 3,
s.
nally, a layout must be generated for the sized schemat 7, 10].
ics. Of these three major steps, this paper focuses on Closed sizing systems are all equation based; that
the problem of analog sizing. is, the knowledge about the available topologies is pro
Analog sizing is a very complicated, time-con vided as analytical design equations. The associated
suming task whose automation has drawn strong atten design equations for new topologies must be generated
tion in recent years, where several tools and method - a task for only real analog design experts to tackle.
ologies have evolved [1-8]. Two basic reasons lie be Another drawback relating to closed systems is that
hind these developments: a) market pressure to reduce they do not allow the exploration oftopology enhance
the design cost of the analog components of modem ments as conceived by designers with some expertise.
analog-digital ASICs and b) the need for custom ana Some of the drawbacks of closed systems are over
log design to be available to ASIC system designers. come by the approaches in [9, 11 ], which are also equa
Most previously reported approaches for automated tion based. The distinctive feature is that some of the
analog cell design are closed systems covering only design equations for new topologies are automatically
a limited number (though not necessarily small, see generated via auxiliary symbolic analysis tools [9, 12].
for instance [1]) of schematics. Some tools work on Expert concourse is not further required to that end.
a flat schematic library where topologies are defined Unfortunately, symbolic analysis tools provide equa
at the device-level [1, 6, 8, 9]. In others [3, 5, 7, 10] tions for neither DC nor large signal transient charac
architectures are defined at the conceptual level as a teristics, whose associated design equations must still
3
180 Medeiro, Rodrfguez-Macfas, Fernandez. Dom(nguez-Castro, Huertas and Rodrfguez-Vazquez
be manually provided. Hence, the methodology is only analog output buffer, which were sized using the pro
partially open. Furthermore, the level of complexity for posed methodology, fabricated in different CMOS
AC automatic modeling is limited by the capabilities technologies, and whose performance was corrobo
of symbolic analysis tools (currently, about 15 MOS rated from actual silicon prototypes. The proposed
transistors using high-frequency MOST models and technique is also extended to design for low variability
workstation standard configurations). Consequently, incorporating mismatching information in the design
this approach is not the most suitable for the auto procedure. This is illustrated in the design of a CMOS
mated sizing of complex analog building blocks (for folded-cascode operational amplifier.
instance, fully-differential opamps), or for applications
where large signal specifications play a major role, for 2. Some Generalities on Optimization-Based
instance, oversampled modulators for high resolution Sizing
AID converters [ 13].
Whether closed or open, equation-based systems Analog sizing is a constructive procedure to map cell
have a common drawback in that sizing is carried out specifications into design parameter values. Design
using simplified analytical descriptions of the blocks. specifications are given a broad meaning here which
Hence, manual fine-tuning using an electrical sim includes constraints on the electrical performance pa
ulator and detailed MOS transistor models may be rameters of the cell as well as design objectives. Let us
necessary once rough automated sizing is completed. consider for illustration purposes the output buffer of
This drawback is overcome in the so-called simulation figure 1, one of the examples covered in this paper. A
based systems [14], which also reduce sizing to a con possible specification set for this circuit could include
constraints on its DC gain (Ao > target), input capaci
strained optimization problem, and aim to solve it by
following an iterative procedure built around an elec tance (C;n <target), 3-dB frequency (f3d8 >target),
and output voltage range (target < OS < target), in
trical simulator. No design equations are required in
addition to the design objective of minimum possible
these approaches; the design parameters are updated
power consumption. With regards to the design param
at each iteration based on the results provided by sim
eters, these include transistor dimensions and passive
ulations with detailed transistor models. Thus, they
component values.
are intrinsically open. A representative example of
In a generic circuit, the design parameters can
this methodology is DELIGHT. SPICE [14] where DE
be viewed as components of a vector xT
LIGHT (a general algorithmic optimization tool) and
SPICE are combined. Also, advanced electrical simu {x 1, x2, ... , x N} defining a multidimensional de
sign space. Thus, performance parameters and the
lators, like HSPICE [ 15], incorporate optimization rou
tines. However, the optimization routines in both tools
search for a local solution, and consequently are typ
ically used to redesign cells whose performance spec
ifications are close to the design goals (for instance,
technology updating of a cell library), but are inappro
priate to size analog cells from scratch. This is a real
challenge in analog design automation and requires the
development of other techniques.
This paper presents a simulation-based approach for
global sizing of arbitrary topology analog cells us
ing statistical optimization. We demonstrate that by
combining proper cost function formulation and in
novative optimization heuristics complex cells are de
signed starting from arbitrary initial points, within rea
sonable CPU times and with no designer interaction
required - a very appealing feature for ASIC appli
cations. We present results obtained for two fully
differential CMOS opamps, a comparator and an Fig. 1. A CMOS output buffer.
4
Global Design of Analog Cells using Statistical Optimization Techniques 181
features involved in design objectives are given as introduces additional complications to the analyti
functions of x; referring again to the example cal solution process.
of figure I: A (x),C;n(x).fadB(x),OS(x), and Due to these difficulties, analog circuits are most
0
Power(x). Then the problem of sizing is formulated as conveniently sized by using an iterative, dynamic pro
a constrained optimization problem; in particular, for cess. This concept is illustrated in figure 2: starting
the case of the buffer of figure I , from an initial design parameter estimate, x0, a dis
crete sequence of movements (represented generically
minimize Power (x) as ~xn) is performed through the design parameter
A (x) > target space until an equilibrium solution point x• is found.
0
subjected to C1n(x) < target (I) A key component of this iterative loop is process
!adn(x) > target management: the calculation of the direction and mag
target < OS(x) < target nitude of the movement ~Xn to be made at each itera
tion. In manual design, ~Xn is chosen by the designer
Unfortunately, even for elementary analog cells like based on his/her knowledge of the circuit structure be
that shown in figure I, the analytical solution to the ing sized - a difficult and time-consuming task even
sizing problem is not possible due, among other fac for experienced analog designers. In automated de
tors, to the following: sign, the selection of ~Xn must be performed by the
• Design equations, i.e., functional relationships computer based on the evaluation of some critical cir
among performance parameters and design objec cuit performance indicators. A convenient approach to
tives on one hand, and design parameters on the do this is to recast the problem formulation as a cost
other, are very difficult to obtain accurately. function 4i(x) which quantifies the degree of achieve
• These relationships are typically highly nonlinear ment of the design goals and their relation to the design
and, consequently, unsolvable analytically. A fur parameters. Thus, the parameter updating to be done
ther complication arises due to the large dimensions for the subsequent iteration ~Xn is selected at each
of the design and the specification spaces. iteration using functional analysis data of 4i(x). This
• The need to minimize some functions forces the cal approach also provides simple and accurate criteria to
culation of first and second derivatives and hence finish the sizing process at points where the cost func
tion is either maximized or minimized.
In the simplest case, ~Xn is calculated by using
pieces of information calculated only at Xn· However,
as demonstrated in this paper, the use of additional in
formation from previous points, at time instances n-1,
n - 2, etc., may produce more robust solutions of the
sizing problem, in the sense of yielding cells whose
specifications have lower variability when statistical
variations of the technological parameters are taken
@! into account. In this more general case, the updating
YF.S:
process is described as a high-order nonlinear discrete
time system,
(a) =···o;;~·g;;p.;x.c;s·~ianagen;cn.················
As stated in the introduction, we will assume that
~ ~ performance evaluations in figure 2 (equivalently, the
calculation of performance specification values and the
manual managemcr·u au1oma1ed management values of the features involved in the design equations
•non••••••••••••••••,.,.•••••••••••••
as functions of x) are made using electrical simulation
(b) PARAMETER UJ"'ATINC and detailed transistor models to guarantee accuracy
of the sizing process. Many different alternative im
Fig. 2. Iterative analog cell sizing: (a) general concept; (b) manual
and automated design updating management. plementations of figure 2 are possible depending on:
5
182 Medeiro, Rodrfguez-Macfas, Fernandez. Domfnguez-Castro, Huertas and Rodrfguez-Vdzquez
a) formulation ofthecost function itself, b) the updating allowed. Hence, if any setting of the design parame
procedure. Two major alternatives can be roughly iden ters (equivalently, any point of the design parameter
tified, depending of the functional structure of S[ •) space) does not satisfy one strong restriction, it must
in (2): be rejected immediately.
• Deterministic, incremental techniques where .6x,. • Weak restrictions: These are the typical perfor
calculation uses information about the derivatives mance specifications required of analog building
of the cost function. This is an important draw blocks, i.e., A0 > 80dB. Unlike strong restrictions,
back since analytical expressions for the cost func weak restrictions allow some relaxation of the tar
tion and its derivatives as functions of the design get parameters, making such circuit sizings which
parameters are not commonly available, so that the do not meet such specifications acceptable.
derivatives must be calculated by numerical interpo • Design objectives: Stated as the minimi7.ation
lation. Another major drawback is that only .6x,. (maximization reduces to this case by either chang
values which lower the cost function are considered. ing the sign or using the inverse of the function to
Hence, the optimization process is easily trapped in maximize) of some performance features,
local minima, rendering it very suitable only for fine
adjustment of the design. minimize Y>~~, (x) 1 ::; i ::; P (3)
• Statistical techniques, where .6xn is calculated at
random and hence requires no information about the for instance, minimize -GB of an opamp (equiva
cost function derivatives. lently, maximize GB), where GB denotes the gain
Parameter updating in deterministic techniques is bandwidth product; or minimize the occupied area
done only in the direction which lowers the cost func of the circuit.
tion. This makes them very sensitive to the starting Mathematically, the fulfillment of these specifi
point and hence inadequate for global circuit sizing. cations can be formulated as a multi-objective con
This is overcome using statistical optimization tech strained optimization problem,
niques where movements in the design space are done
heuristically, following statistical optimization princi minimize !Y>~~, (x }, 1 ::; i ::; P
ples [16]. The price to pay for an independent initial
point is a larger number of iterations and hence longer y.;(x) ;::: Y.; or Ya;(x) ::; Y..;,
CPU times. However, as shown here, proper formu
lation of the cost function, the movement generator, 1 ::;j::; Q
and the cooling schedule, adapted to the nature of ana subjected to
log synthesis, palliates the high computational cost and Ywk(x) 2:: Ywk or Ywk(x) ::; Ywk•
thus provides a convenient methodology for global de 1 ::;k::; R
sign of analog cells.
(4)
where Y>~~; denotes the value of the i-th design objec
tive; Y•i and Ywk denote values of the circuit speci
3. Cost Function Formulation fications (subscripts s and w denote strong and weak
specifications, respectively); and Y.; and Ywk are the
A first step towards devising a tool for automated sizing corresponding targets (for instance, A0 ;::: 80dB, set
of analog cells using statistical optimization is to for tling time ::; O.lJ.!s).
malize the setting of performance specifications. In a The cost function is defined in the minimax sense as
more general case, three different specification classes follows,
must be considered:
• Strong restrictions: These are specifications minimize ~(x)
whose fulfillment is considered essential by the (5)
designer; for instance, the phase margin of an = max{ F>~~(Y>~~;), F.;(Y.;), Fwk(Ywk)}
opamp must be larger than 0 (PM > 0} for sta
bility [17]. No relaxation of the specified value is where the partial cost functions F>~~( • ),F.j( • ),
6
Global Design of Analog Cells using Statistical Optimization Techniques 183
and Fwlc( •) are defined as vector, .1.x.,, is randomly generated at each iteration.
The value of the cost function is calculated at the new
-L
w; log(IY>~o;/), parameter space point and compared to the previous
i one. The new point is accepted if the cost function has
F.i(Y.J) K.J(Y•J• Ysi) (6) a lower value. Unlike deterministic techniques, it may
f::) also be accepted if the cost function increases, accord
Fwlc(Ywk) -Kwk(Ywk> Ywk) log ( ing to a probability function,
(8)
where w; (called weight parameters for the design ob
jectives) is a positive (alternatively negative) real num depending on a control parameter, T. The random
ber if Y>~oi is positive (alternatively negative), and for character of movements and the statistical acceptance
K,j( •) and Kwk( •) we have of those which increase the cost function enable es
caping from local minima and hence wide exploration
-oo, if strong of the design space. This probability of acceptance
{ restriction holds changes during the optimization process, being high at
oo, otherwise the beginning (for large T) and decreasing as the system
cools (decreasing T). This is the general concept lying
if weak behind simulated annealing optimization techniques
restriction holds a process whose name is justified by its analogies to the
otherwise physical annealing in solids [ 16]. The tool proposed
(7) herein incorporates new heuristics relating to both pa
rameter updating and the cooling schedule itself, as
where k~c (weight parameters assigned to weak restric explained below.
tions) is a positive (alternatively negative) real num
ber if the weak specification is of ~ (alternatively :::;) 4.1. Cooling Schedule
type. Weight parameters are used to give priority to the
associated design objectives and weak specifications. Cooling schedule refers to the strategy used to mod
As shown in the cost function formulation, only rela ify the temperature while the process evolves. Unlike
tive magnitude of the weight parameters of the same
type makes sense. In (7) weak specifications are as
sumed positive. Sign criteria is reversed for negative
specifications.
Strong restrictions are checked first at each itera
tion. If any of them are not met, the corresponding
movement must be rejected. Otherwise, weak restric
tions are examined. Weak restrictions have priority
over design objectives. If some weak restriction is not
fulfilled, the cost function is built only with their con
tribution. Hence, if no circuit sizing is able to cover all
weak specifications, the optimization process will pro
vide results as close as possible. Once all of them are
met, the design objectives are evaluated and their in
fluence in the cost function guides their maximization
or minimization.
4. Parameter Updating and Process Management
Figure 3 shows a block diagram illustrating the opera
tion flow in the proposed methodology. The updating Fig. 3. Operation flow in the proposed methodology.
7
