Analog Circuit Design: RF Analog-to-Digital Converters; Sensor and Actuator Interfaces; Low-Noise Oscillators, PLLs and Synthesizers

416 Pages·1997·14.56 MB·English

by  Thorsten Baumheinrich

ANALOG CIRCUIT DESIGN
Analog Circuit Design
RF Analog-to-Digital Converters;
Sensor and Actuator Interfaces;
Low-Noise Oscillators, PLLs and
Synthesizers
Edited by
RUDY J. VAN DE PLASSCHE
Philips Research Laboratories,
Eindhoven, The Netherlands
JOHAN H. HUIJSING
T.U. Delft, The Netherlands
and
WILLY SANSEN
K.U. Leuven, Heverlee, Belgium
Springer-Science+Business Media, B.Y.
A c.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4419-5185-4 ISBN 978-1-4757-2602-2 (eBook)
DOI 10.1007/978-1-4757-2602-2
Printed on acid-free paper
All Rights Reserved
© 1997 Springer Science+Business Media Dordrecht
Originally published by Kluwer Academic Publishers in 1997.
Softcover reprint of the hardcover 1s t edition 1997
No part of the material protected by this copyright notice may be reproduced or
utilized in any form or by any means, electronic or mechanical,
including photocopying, recording or by any information storage and
retrieval system, without written permission from the copyright owner.
Table of Contents
Preface vii
Part I: RF Analog-to-Digital Converters
Introduction 1
Design of a Silicon Bipolar Track&Hold IC for Igsample/s and 10 bit
Linearity over the full Nyquist Band
Thorsten Baumheinrich, Bernd Pregardier, Ulrich Langmann 3
Power and Scaling Rules of CMOS High-Speed AID Converters
Ardie GW Venes and Rudy van de Plassche .................................................................. 25
An Embedded 170-mW lO-BIT 50-MS/s CMOS ADC IN I-mm2
Klaas Bult and Aaron Buchwald ..................................................................................... 49
Architectures and Circuits for AID and D/A Conversion in CMOS
Integrated Systems for Telecom Applications
Jan Sevenhans and Zhong-Yuan Chang 65
A 12 bit, 50 Msample/s Cascaded Folding & Interpolating ADC
Pieter Vorenkamp and Raf Roovers 89
Linearizing a 128 Msample/s ADC
Robert Jewett, Ken Poulton, Kuo-Chiang Hsieh and Joey Doernberg 105
Part II: Sensor and Actuator Interfaces
Introduction 121
Advances in State-of-the-Art in Smart Sensor Signal Conditioning
Janusz Bryzek and Ali Rastegar .. 123
Low-Power Sensor Interfaces
Ted Smith, Jean-Paul Bardyn and Michel Chevroulet 151
Capacitive Interfaces for Monolithic Integrated Sensors
Bernhard Boser .............................................................................................................. 177
Low-Cost Interfaces for Sensors and Sensor Systems
Frank van der Goes and Gerard Meijer 197
Integrated Sensor Systems in CMOS Technology
Bedrich Hosticka ........................................................................................................... 219
vi
Compensation and Calibration of IC Microsensors
Andreas Haberli and Henry Baltes 243
Part III -Low-noise oscillators, PLL's and Synthesizers
Introduction 269
How Phase Noise Appears in Oscillators
Asad Abidi ..................................................................................................................... 271
Synthesizer Architectures
Cicero V aucher .............................................................................................................. 291
Fully Integrated Low Phase-Noise VCOs: from Post-Processing to
Standard CMOS
Michiel Steyaert and Jan Craninckx 331
Modeling and Simulation of Jitter in Phase-Locked Loops
Ken Kundert 359
Phase Noise, Signal Power and Current Consumption in CMOS Colpitts
Oscillators
Qiuting Huang 381
Noise in Fully Integrated PLL's
G. Palmisano, M. Paparo, F. Torrisi and P. Vita 401
Preface
This book contains the extended and revised versions of the talks of all
speakers presented at the sixth AACD Workshop held in Villa Olmo,
April 2-4 1997 Como, Italy. The local chairman was Pietro Erratico and
the organization was performed by Isabella De Quattro both of SGS
Thomson Microelectronics Cornareda and Agrate Brianza Italy. The
program consisted of six tutorials per day during three days. These
tutorials were presented by experts in the field to give state of the art
information.
Program topics for the following workshop are selected by the audience at
the end of the workshop. The program committee, consisting of 10han
Huijsing of Delft University of Technology, Willy Sansen of Katholieke
Universiteit Leuven and Rudy van de Plassche of Philips Research Labs
and University of Technology Eindhoven elaborates the selected topics
into a three day program and selects the experts in the field for
presentation.
Each AACD Workshop has given rise to the publication of a book by
Kluwer entitled "Analog Circuit Design". This series of six books in a row
provides a valuable overview of all analog circuit techniques concerning
design, CAD, simulation and device modeling and can be seen as a
reference to those involved in analog circuits.
The aim of the workshop is to brainstorm on new and valuable design
ideas in the area of analog circ1,lit design. It is the hope of the program
committee that this sixth book continues the tradition of a valuable
contribution to the insight in analog circuit design in Europe and the rest
of the world.
Rudy 1. van de Plassche
University of Technology Eindhoven.
vii
RF ANALOG-TO-DIGITAL CONVERTERS
RJ. van de Plassche
Preface
The application of digital techniques to process analog
modulated rf signals in radio receivers requires high linearity
and high-resolution analog-to-digital converters. In portable
applications these converters must have an extreme low-power
consumption to allow a long standby time. In low-cost signal
processing applications these converters are combined with a
digital signal processing system onto a single chip. Today digital
signal processing systems use advanced CMOS technologies
requiring the analog-to-digital converter to be implemented in
the same (digital) technology. Such an implementation requires
special circuit techniques. Furthermore the susceptibility of
converters to ground bounce or digital noise is an important
design criterion. In this session different converters and
conversion techniques will be described that are optimized for
receiver applications.
In the first paper by Baumheinrich et aI, design criteria for a 1
GS/s track and hold circuit are given. The bipolar circuit is able
to sample analog frequencies up to 500 MHz with distortion
levels below 60 dB at full-scale input.
The second paper by Venes et al describes power and scaling
rules for high-speed CMOS analog-to-digital converters using
folding and interpolation architectures. These 8-bit CMOS
converters are optimized for low-power and high linearity in a
digital 0.5 and 0.35 micron digital CMOS technology to be
combined with digital signal processing circuitry on the same
chip. Scaling down a technology mostly results in a better
matching between two adjacent equally sized MOS devices.
R.l. van de Plassche et al. (eds.), Analog Circuit Design, 1-2.
© 1997 Kluwer Academic Publishers.
2
Scaling improves high frequency signal performance at lower
power consumption.
The third paper by Bult et al describes a 10-bit system analog
to-digital converter implemented in a 0.5-micron digital CMOS
technology. A special technique is used in the input
:iV~raging
stages of the converter to increase the DNL with 4-bits and the
INL with 2-bits. A cascaded folding architecture is
implemented. No trimming of circuits is applied to reduce cost.
The fourth paper by Chang et al describes various architectures
of analog-to-digital and digital-to-analog converters applied in
telecommunication systems. Especially the design
considerations for high-speed and high resolution pipelined
converters is emphasized.
The fifth paper by Vorenkamp et al describes a l2-bit bipolar
cascaded folding and interpolating analog-to-digital converter
suitable for applications in digital receiver systems. Special
attention has been paid to linearity at high input frequencies. 75
dB SFDR has been obtained over an input frequency range of 50
MHz.
The last paper in this session describes special on-chip
techniques to obtain an extreme small DNL of 0.05 LSB.
Standard converter architecture is used but dynamic element
matching and self-calibration circuits are added to increase
linearity. As a result the distortion components in a l2-bit
converter are reduced to more than 105 dB below full-scale
input.
Ie
Design of a Silicon Bipolar Track&Hold for
1GSample/s and 10 bit Linearity over the
full Nyquist Band
Thorsten Baumheinrich Bernd Pregardier
1, 1,2,
Ulrich Langmann
1
Ruhr-Universitat Bochum, D-44780 Bochum,
1
Germany
now with Rockwell Semiconductor Systems,
2
Newport Beach, CA 92658-8902, USA
1. INTRODUCTION
This chapter discusses the design of a silicon bipolar Track&Hold IC
achieving a linearity of 10 effective bits over the full Nyquist band for
sampling frequencies up to 1 GSample/s. Suitable circuit techniques
which were implemented to assure this performance will be presented
in detail, as well as the simulation techniques that were applied
throughout the design process. We will complete this chapter with a
presentation of the measurement setup and the measured performance
characteristics.
Track&Hold circuits are key components for fast and accurate data
conversion and signal processing systems. As frontends for analog-to
digital converters, they significantly determine the properties of the
whole conversion system in terms of operating speed and bandwidth.
Moreover, the signal quality, which is here referred to as linearity and
effective number of bits, and thus the data integrity in the digital part
of a signal processing system is often limited also by the properties of
the Track&Hold circuit.
3
R. J. van de Plassche et al. (eds.), Analog Circuit Design, 3-24.
© 1997 Kluwer Academic Publishers.
4
The reason for this is, that most of the distortion which is induced by
the analog path in front of the (last) quantisation stage of a converter
mostly cannot be corrected by digital signal processing, because the
implementation of the necessary functions disagrees with system
requirements such as complexity, chip area, cost and power
consumption.
This is particularly true for very fast conversion systems that are
operated at the speed of some hundred megahertz and still need higher
levels of linearity and analog bandwidth.
2. DESIGN CONSTRAINTS
One of the most challenging issues especially for the design of high
speed Track&Hold circuits is to develop a compromise between the
power dissipation demands, the analog bandwidth and the linearity of
the circuit.
A further relevant characteristic is the allowable variation of the clock
frequency for a given linearity level, which we refer to as digital
bandwidth. This feature is of great importance for applications that
require different sampling frequencies but do not allow interpolation
between the sampled voltage values.
Neff fsample I fan:l!o!:! I VPSR I P dissipation I Technology
10.5 300MHzI 50 MHz I +/- 250 mV I 30mWI BiCMOS
See Ref. [1]
10 250MHzI 70 MHz I +/- 500 mV I 225 mW I BiCMOS
See Ref. [2]
9 800 MHz I 100 MHz I +/-250 mV I 2.1WI 0.3).lm AIGaAs
See Ref. [3]
wi
5.6 4000 MHz I 200 MHzl n.a·1 5.7 AIGaAs HBT
See Ref. [4]
8.6 1000 MHzl 500MHzI +/-500mVI 440mWI Si-Bipolar
I See Ref. [5]
--
Table I: Performance overview of published Track&Hold circuits